1 from openpower
.simulator
.program
import Program
2 from openpower
.sv
.trans
.pysvp64dis
import load
, dump
3 from openpower
.sv
.trans
.svp64
import SVP64Asm
4 from openpower
.decoder
.power_insn
import Database
, Verbosity
5 from openpower
.decoder
.power_enums
import find_wiki_dir
6 from openpower
.sv
import sv_binutils_fptrans
11 class SVSTATETestCase(unittest
.TestCase
):
13 def _do_tst(self
, expected
):
14 isa
= SVP64Asm(expected
)
16 with
Program(lst
, bigendian
=False) as program
:
17 print ("ops", program
._instructions
)
18 program
.binfile
.seek(0)
19 insns
= load(program
.binfile
)
23 print ("insns", insns
)
24 for i
, line
in enumerate(dump(insns
, verbosity
=Verbosity
.SHORT
)):
25 name
= expected
[i
].split(" ")[0]
26 with self
.subTest("%d:%s" % (i
, name
)):
27 print("instruction", repr(line
), repr(expected
[i
]))
28 self
.assertEqual(expected
[i
], line
,
29 "instruction does not match "
30 "'%s' expected '%s'" % (line
, expected
[i
]))
34 expected
= ['addi 1,5,2',
40 self
._do
_tst
(expected
)
42 def test_1_svshape2(self
):
44 'svshape2 12,1,15,5,0,0'
46 self
._do
_tst
(expected
)
48 def test_2_d_custom_op(self
):
54 self
._do
_tst
(expected
)
56 def test_3_sv_isel(self
):
60 'sv.isel 12,2,3,*483',
64 self
._do
_tst
(expected
)
66 def test_4_sv_crand(self
):
68 'sv.crand *16,*2,*33',
71 self
._do
_tst
(expected
)
73 def test_5_setvl(self
):
78 self
._do
_tst
(expected
)
80 def test_6_sv_setvl(self
):
82 "sv.setvl 5,4,5,0,1,1",
83 "sv.setvl 63,35,5,0,1,1",
85 self
._do
_tst
(expected
)
87 def test_7_batch(self
):
88 "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
102 "sv.fmuls *32,*32,*40",
108 "sv.fmuls *32,*32,*40",
123 "sv.lfs *48,256(16)",
124 "sv.fmuls *40,*32,*40",
126 "sv.fmuls *32,*32,*48",
134 "sv.lfs *48,256(16)",
135 "sv.fmuls *40,*32,*40",
137 "sv.fmuls *32,*32,*48",
154 "sv.fmuls *32,*32,*40",
159 self
._do
_tst
(expected
)
161 def test_8_madd(self
):
167 self
._do
_tst
(expected
)
169 def test_9_fptrans(self
):
170 "enumerates a list of fptrans instruction disassembly entries"
171 db
= Database(find_wiki_dir())
172 entries
= sorted(sv_binutils_fptrans
.collect(db
))
173 dis
= lambda entry
: sv_binutils_fptrans
.dis(entry
, binutils
=False)
174 self
._do
_tst
(list(map(dis
, entries
)))
176 def test_10_vec(self
):
178 "sv.add./vec2 *3,*7,*11",
179 "sv.add./vec3 *3,*7,*11",
180 "sv.add./vec4 *3,*7,*11",
182 self
._do
_tst
(expected
)
184 def test_11_elwidth(self
):
186 "sv.add./dw=8 *3,*7,*11",
187 "sv.add./dw=16 *3,*7,*11",
188 "sv.add./dw=32 *3,*7,*11",
189 "sv.add./sw=8 *3,*7,*11",
190 "sv.add./sw=16 *3,*7,*11",
191 "sv.add./sw=32 *3,*7,*11",
192 "sv.add./dw=8/sw=16 *3,*7,*11",
193 "sv.add./dw=16/sw=32 *3,*7,*11",
194 "sv.add./dw=32/sw=8 *3,*7,*11",
195 "sv.add./w=32 *3,*7,*11",
196 "sv.add./w=8 *3,*7,*11",
197 "sv.add./w=16 *3,*7,*11",
199 self
._do
_tst
(expected
)
201 def test_12_sat(self
):
203 "sv.add./satu *3,*7,*11",
204 "sv.add./sats *3,*7,*11",
206 self
._do
_tst
(expected
)
208 def test_12_mr_r(self
):
210 "sv.add./mrr/vec2 *3,*7,*11",
211 "sv.add./mr/vec2 *3,*7,*11",
212 "sv.add./mrr *3,*7,*11",
213 "sv.add./mr *3,*7,*11",
215 self
._do
_tst
(expected
)
217 def test_13_RC1(self
):
219 "sv.add/ff=RC1 *3,*7,*11",
220 "sv.add/pr=RC1 *3,*7,*11",
221 "sv.add/ff=~RC1 *3,*7,*11",
222 "sv.add/pr=~RC1 *3,*7,*11",
224 self
._do
_tst
(expected
)
226 def test_14_rc1_ff_pr(self
):
228 "sv.add./ff=eq *3,*7,*11",
229 "sv.add./ff=ns *3,*7,*11",
230 "sv.add./pr=eq *3,*7,*11",
231 "sv.add./pr=ns *3,*7,*11",
233 self
._do
_tst
(expected
)
235 def test_15_predicates(self
):
237 "sv.add./m=r3 *3,*7,*11",
238 "sv.add./m=1<<r3 *3,*7,*11",
239 "sv.add./m=~r10 *3,*7,*11",
240 "sv.add./m=so *3,*7,*11",
241 "sv.add./m=ne *3,*7,*11",
242 "sv.add./m=lt *3,*7,*11",
244 "sv.extsw/m=r30 3,7",
245 "sv.extsw/dm=~r30/sm=r30 3,7",
246 "sv.extsw/dm=eq/sm=gt 3,7",
247 "sv.extsw/sm=~r3 3,7",
248 "sv.extsw/dm=r30 3,7",
250 self
._do
_tst
(expected
)
252 def test_15_els(self
):
254 "sv.stw/els *4,16(2)",
255 "sv.lfs/els *1,256(4)",
257 self
._do
_tst
(expected
)
259 def test_16_bc(self
):
260 # hilarious. this should be autogenerated from a sequence
261 # of lists of options. it's a lot of frickin options.
262 lists
= [[None, 'all'],
263 [None, 'm=r3/sz', 'm=r3/snz'],
264 #[None, 'vs', 'vsi', 'vsb', 'vsbi'],
265 [None, 'ctr', 'cti'],
271 for options
in itertools
.product(*lists
):
272 options
= list(filter(lambda x
:x
, options
))
273 options
.sort() # otherwise chaos!
274 if len(options
) != 0:
275 options
= [''] + options
# trick to make a "/" at the front
276 print ("option", options
)
277 option
= "sv.bc%s 12,*1,0xc" % "/".join(options
)
278 expected
.append(option
)
279 #_old_handcrafted_expected = [
281 "sv.bc/all 12,*1,0xc",
282 "sv.bc/snz 12,*1,0xc",
283 "sv.bc/m=r3/snz 12,*1,0xc",
284 "sv.bc/m=r3/sz 12,*1,0xc",
285 "sv.bc/all/sl/slu 12,*1,0xc",
286 "sv.bc/all/lru/sl/slu/snz 12,*1,0xc",
287 "sv.bc/all/lru/sl/slu/snz/vs 12,*1,0xc",
288 "sv.bc/all/lru/sl/slu/snz/vsi 12,*1,0xc",
289 "sv.bc/all/lru/sl/slu/snz/vsb 12,*1,0xc",
290 "sv.bc/all/lru/sl/slu/snz/vsbi 12,*1,0xc",
291 "sv.bc/all/ctr/lru/sl/slu/snz 12,*1,0xc",
292 "sv.bc/all/cti/lru/sl/slu/snz 12,*1,0xc",
293 "sv.bc/all/ctr/lru/sl/slu/snz/vsb 12,*1,0xc",
295 self
._do
_tst
(expected
)
297 def test_17_vli(self
):
299 "sv.add/ff=RC1/vli 3,7,11",
301 self
._do
_tst
(expected
)
303 if __name__
== "__main__":