src/openpower/sv/trans/test_pysvp64dis.py

   1 from openpower.simulator.program import Program
   2 from openpower.sv.trans.pysvp64dis import load, dump
   3 from openpower.sv.trans.svp64 import SVP64Asm
   4 from openpower.decoder.power_insn import Database, Verbosity
   5 from openpower.decoder.power_enums import find_wiki_dir
   6 from openpower.sv import sv_binutils_fptrans
   7 import unittest
   8 import itertools
   9 import sys
  10
  11 class SVSTATETestCase(unittest.TestCase):
  12
  13     def _do_tst(self, expected):
  14         isa = SVP64Asm(expected)
  15         lst = list(isa)
  16         with Program(lst, bigendian=False) as program:
  17             print ("ops", program._instructions)
  18             program.binfile.seek(0)
  19             insns = load(program.binfile)
  20             #for insn in insns:
  21                 #print ("insn", insn)
  22             insns = list(insns)
  23             print ("insns", insns)
  24             for i, line in enumerate(dump(insns, verbosity=Verbosity.SHORT)):
  25                 name = expected[i].split(" ")[0]
  26                 with self.subTest("%d:%s" % (i, name)):
  27                     print("instruction", repr(line), repr(expected[i]))
  28                     self.assertEqual(expected[i], line,
  29                                      "instruction does not match "
  30                                      "'%s' expected '%s'" % (line, expected[i]))
  31
  32
  33     def test_0_add(self):
  34         expected = ['addi 1,5,2',
  35                     'add 1,5,2',
  36                     'add. 1,5,2',
  37                     'addo 1,5,2',
  38                     'addo. 1,5,2',
  39                         ]
  40         self._do_tst(expected)
  41
  42     def test_1_svshape2(self):
  43         expected = [
  44                     'svshape2 12,1,15,5,0,0'
  45                         ]
  46         self._do_tst(expected)
  47
  48     def test_2_d_custom_op(self):
  49         expected = [
  50                     'fishmv 12,2',
  51                     'fmvis 12,97',
  52                     'addpcis 12,5',
  53                         ]
  54         self._do_tst(expected)
  55
  56     def test_3_sv_isel(self):
  57         expected = [
  58                     'sv.isel 12,2,3,33',
  59                     'sv.isel 12,2,3,*33',
  60                     'sv.isel 12,2,3,*483',
  61                     'sv.isel 12,2,3,63',
  62                     'sv.isel 12,2,3,*99',
  63                         ]
  64         self._do_tst(expected)
  65
  66     def test_4_sv_crand(self):
  67         expected = [
  68                     'sv.crand *16,*2,*33',
  69                     'sv.crand 12,2,33',
  70                         ]
  71         self._do_tst(expected)
  72
  73     def test_5_setvl(self):
  74         expected = [
  75                     "setvl 5,4,5,0,1,1",
  76                     "setvl. 5,4,5,0,1,1",
  77                         ]
  78         self._do_tst(expected)
  79
  80     def test_6_sv_setvl(self):
  81         expected = [
  82                     "sv.setvl 5,4,5,0,1,1",
  83                     "sv.setvl 63,35,5,0,1,1",
  84                         ]
  85         self._do_tst(expected)
  86
  87     def test_7_batch(self):
  88         "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
  89         expected = [
  90                     "addi 2,2,0",
  91                     "addis 9,2,0",
  92                     "addi 9,9,0",
  93                     "rlwinm 7,7,2,0,29",
  94                     "mulli 0,7,31",
  95                     "add 10,6,0",
  96                     "setvl 0,0,8,1,1,0",
  97                     "addi 16,4,124",
  98                     "lfiwax 0,0,5",
  99                     "addi 5,3,64",
 100                     "sv.lfs *32,256(4)",
 101                     "sv.lfs *40,256(5)",
 102                     "sv.fmuls *32,*32,*40",
 103                     "sv.fadds 0,*32,0",
 104                     "addi 5,3,192",
 105                     "addi 4,4,128",
 106                     "sv.lfs *32,256(4)",
 107                     "sv.lfs *40,256(5)",
 108                     "sv.fmuls *32,*32,*40",
 109                     "sv.fsubs 0,0,*32",
 110                     "addi 4,4,-128",
 111                     "stfs 0,0(6)",
 112                     "add 6,6,7",
 113                     "addi 4,4,4",
 114                     "addi 0,0,15",
 115                     "mtspr 288,0",
 116                     "addi 8,0,4",
 117                     "lfiwax 0,0,9",
 118                     "lfiwax 1,0,9",
 119                     "addi 5,3,64",
 120                     "add 5,5,8",
 121                     "sv.lfs *32,256(5)",
 122                     "sv.lfs *40,256(4)",
 123                     "sv.lfs *48,256(16)",
 124                     "sv.fmuls *40,*32,*40",
 125                     "sv.fadds 0,0,*40",
 126                     "sv.fmuls *32,*32,*48",
 127                     "sv.fsubs 1,1,*32",
 128                     "addi 5,3,192",
 129                     "subf 5,8,5",
 130                     "addi 4,4,128",
 131                     "addi 16,16,128",
 132                     "sv.lfs *32,256(5)",
 133                     "sv.lfs *40,256(4)",
 134                     "sv.lfs *48,256(16)",
 135                     "sv.fmuls *40,*32,*40",
 136                     "sv.fsubs 0,0,*40",
 137                     "sv.fmuls *32,*32,*48",
 138                     "sv.fsubs 1,1,*32",
 139                     "addi 4,4,-128",
 140                     "addi 16,16,-128",
 141                     "stfs 0,0(6)",
 142                     "add 6,6,7",
 143                     "stfs 1,0(10)",
 144                     "subf 10,7,10",
 145                     "addi 8,8,4",
 146                     "addi 4,4,4",
 147                     "addi 16,16,-4",
 148                     "bc 16,0,-0xb4",
 149                     "addi 5,3,128",
 150                     "addi 4,4,128",
 151                     "lfiwax 0,0,9",
 152                     "sv.lfs *32,256(4)",
 153                     "sv.lfs *40,256(5)",
 154                     "sv.fmuls *32,*32,*40",
 155                     "sv.fsubs 0,0,*32",
 156                     "stfs 0,0(6)",
 157                     "bclr 20,0,0",
 158                         ]
 159         self._do_tst(expected)
 160
 161     def test_8_madd(self):
 162         expected = [
 163                     "maddhd 5,4,5,3",
 164                     "maddhdu 5,4,5,3",
 165                     "maddld 5,4,5,3",
 166                         ]
 167         self._do_tst(expected)
 168
 169     def test_9_fptrans(self):
 170         "enumerates a list of fptrans instruction disassembly entries"
 171         db = Database(find_wiki_dir())
 172         entries = sorted(sv_binutils_fptrans.collect(db))
 173         dis = lambda entry: sv_binutils_fptrans.dis(entry, binutils=False)
 174         self._do_tst(list(map(dis, entries)))
 175
 176     def test_10_vec(self):
 177         expected = [
 178                     "sv.add./vec2 *3,*7,*11",
 179                     "sv.add./vec3 *3,*7,*11",
 180                     "sv.add./vec4 *3,*7,*11",
 181                         ]
 182         self._do_tst(expected)
 183
 184     def test_11_elwidth(self):
 185         expected = [
 186                     "sv.add./dw=8 *3,*7,*11",
 187                     "sv.add./dw=16 *3,*7,*11",
 188                     "sv.add./dw=32 *3,*7,*11",
 189                     "sv.add./sw=8 *3,*7,*11",
 190                     "sv.add./sw=16 *3,*7,*11",
 191                     "sv.add./sw=32 *3,*7,*11",
 192                     "sv.add./dw=8/sw=16 *3,*7,*11",
 193                     "sv.add./dw=16/sw=32 *3,*7,*11",
 194                     "sv.add./dw=32/sw=8 *3,*7,*11",
 195                     "sv.add./w=32 *3,*7,*11",
 196                     "sv.add./w=8 *3,*7,*11",
 197                     "sv.add./w=16 *3,*7,*11",
 198                         ]
 199         self._do_tst(expected)
 200
 201     def test_12_sat(self):
 202         expected = [
 203                     "sv.add./satu *3,*7,*11",
 204                     "sv.add./sats *3,*7,*11",
 205                         ]
 206         self._do_tst(expected)
 207
 208     def test_12_mr_r(self):
 209         expected = [
 210                     "sv.add./mrr/vec2 *3,*7,*11",
 211                     "sv.add./mr/vec2 *3,*7,*11",
 212                     "sv.add./mrr *3,*7,*11",
 213                     "sv.add./mr *3,*7,*11",
 214                         ]
 215         self._do_tst(expected)
 216
 217     def test_13_RC1(self):
 218         expected = [
 219                     "sv.add/ff=RC1 *3,*7,*11",
 220                     "sv.add/pr=RC1 *3,*7,*11",
 221                     "sv.add/ff=~RC1 *3,*7,*11",
 222                     "sv.add/pr=~RC1 *3,*7,*11",
 223                         ]
 224         self._do_tst(expected)
 225
 226     def test_14_rc1_ff_pr(self):
 227         expected = [
 228                     "sv.add./ff=eq *3,*7,*11",
 229                     "sv.add./ff=ns *3,*7,*11",
 230                     "sv.add./pr=eq *3,*7,*11",
 231                     "sv.add./pr=ns *3,*7,*11",
 232                         ]
 233         self._do_tst(expected)
 234
 235     def test_15_predicates(self):
 236         expected = [
 237                     "sv.add./m=r3 *3,*7,*11",
 238                     "sv.add./m=1<<r3 *3,*7,*11",
 239                     "sv.add./m=~r10 *3,*7,*11",
 240                     "sv.add./m=so *3,*7,*11",
 241                     "sv.add./m=ne *3,*7,*11",
 242                     "sv.add./m=lt *3,*7,*11",
 243                     "sv.add. *3,*7,*11",
 244                     "sv.extsw/m=r30 3,7",
 245                     "sv.extsw/dm=~r30/sm=r30 3,7",
 246                     "sv.extsw/dm=eq/sm=gt 3,7",
 247                     "sv.extsw/sm=~r3 3,7",
 248                     "sv.extsw/dm=r30 3,7",
 249                         ]
 250         self._do_tst(expected)
 251
 252     def test_15_els(self):
 253         expected = [
 254                     "sv.stw/els *4,16(2)",
 255                     "sv.lfs/els *1,256(4)",
 256                         ]
 257         self._do_tst(expected)
 258
 259     def test_16_bc(self):
 260         # hilarious. this should be autogenerated from a sequence
 261         # of lists of options. it's a lot of frickin options.
 262         lists = [[None, 'all'],
 263                  [None, 'm=r3/sz', 'm=r3/snz'],
 264                  #[None, 'vs', 'vsi', 'vsb', 'vsbi'],
 265                  [None, 'ctr', 'cti'],
 266                  #[None, 'sl'],
 267                  #[None, 'slu'],
 268                  #[None, 'lru'],
 269                 ]
 270         expected = []
 271         for options in itertools.product(*lists):
 272             options = list(filter(lambda x:x, options))
 273             options.sort() # otherwise chaos!
 274             if len(options) != 0:
 275                 options = [''] + options # trick to make a "/" at the front
 276             print ("option", options)
 277             option = "sv.bc%s 12,*1,0xc" % "/".join(options)
 278             expected.append(option)
 279         #_old_handcrafted_expected = [
 280         expected = [
 281                     "sv.bc/all 12,*1,0xc",
 282                     "sv.bc/snz 12,*1,0xc",
 283                     "sv.bc/m=r3/snz 12,*1,0xc",
 284                     "sv.bc/m=r3/sz 12,*1,0xc",
 285                     "sv.bc/all/sl/slu 12,*1,0xc",
 286                     "sv.bc/all/lru/sl/slu/snz 12,*1,0xc",
 287                     "sv.bc/all/lru/sl/slu/snz/vs 12,*1,0xc",
 288                     "sv.bc/all/lru/sl/slu/snz/vsi 12,*1,0xc",
 289                     "sv.bc/all/lru/sl/slu/snz/vsb 12,*1,0xc",
 290                     "sv.bc/all/lru/sl/slu/snz/vsbi 12,*1,0xc",
 291                     "sv.bc/all/ctr/lru/snz/sl/slu 12,*1,0xc",
 292                     "sv.bc/all/cti/sl/slu/lru/snz 12,*1,0xc",
 293                     "sv.bc/all/ctr/sl/slu/lru/snz/vsb 12,*1,0xc",
 294                         ]
 295         self._do_tst(expected)
 296
 297 if __name__ == "__main__":
 298     unittest.main()
 299