src/openpower/sv/trans/test_pysvp64dis.py

   1 from openpower.simulator.program import Program
   2 from openpower.insndb.disasm import load, dump
   3 from openpower.insndb.asm import SVP64Asm
   4 from openpower.insndb.core import Database, Style
   5 from openpower.decoder.power_enums import find_wiki_dir
   6 from openpower.sv import sv_binutils_fptrans
   7 import unittest
   8 from io import BytesIO
   9 import itertools
  10 import sys
  11
  12 class SVSTATETestCase(unittest.TestCase):
  13
  14     def _do_tst(self, expected):
  15         isa = SVP64Asm(expected)
  16         lst = list(isa)
  17         with Program(lst, bigendian=False) as program:
  18             print ("ops", program._instructions)
  19             binfile = BytesIO()
  20             program.binfile.seek(0)
  21             binfile.write(program.binfile.read())
  22             program.binfile.seek(0)
  23             binfile.seek(0)
  24             insns = load(binfile)
  25             #for insn in insns:
  26                 #print ("insn", insn)
  27             insns = list(insns)
  28             print ("insns", insns)
  29             for i, line in enumerate(dump(insns, style=Style.SHORT)):
  30                 name = expected[i].split(" ")[0]
  31                 with self.subTest("%d:%s" % (i, name)):
  32                     print("instruction", repr(line), repr(expected[i]))
  33                     self.assertEqual(expected[i], line,
  34                                      "instruction does not match "
  35                                      "'%s' expected '%s'" % (line, expected[i]))
  36
  37
  38     def test_0_add(self):
  39         expected = ['addi 1,5,2',
  40                     'add 1,5,2',
  41                     'add. 1,5,2',
  42                     'addo 1,5,2',
  43                     'addo. 1,5,2',
  44                         ]
  45         self._do_tst(expected)
  46
  47     def test_1_svshape2(self):
  48         expected = [
  49                     'svshape2 12,1,15,5,0,0'
  50                         ]
  51         self._do_tst(expected)
  52
  53     def test_2_d_custom_op(self):
  54         expected = [
  55                     'fishmv 12,2',
  56                     'fmvis 12,97',
  57                     'addpcis 12,5',
  58                         ]
  59         self._do_tst(expected)
  60
  61     def test_3_sv_isel(self):
  62         expected = [
  63                     'sv.isel 12,2,3,33',
  64                     'sv.isel 12,2,3,*33',
  65                     'sv.isel 12,2,3,*483',
  66                     'sv.isel 12,2,3,63',
  67                     'sv.isel 12,2,3,*99',
  68                         ]
  69         self._do_tst(expected)
  70
  71     def test_4_sv_crand(self):
  72         expected = [
  73                     'sv.crand *16,*2,*33',
  74                     'sv.crand 12,2,33',
  75                     'sv.crand/ff=RC1/m=r10 12,2,33',
  76                     'sv.crand/m=r10 12,2,33',
  77                     'sv.crand/m=r10/sz 12,2,33',
  78                     'sv.crand/m=r10/zz 12,2,33',    # SHOULD PASS
  79                         ]
  80         self._do_tst(expected)
  81
  82     def test_5_setvl(self):
  83         expected = [
  84                     "setvl 5,4,5,0,1,1",
  85                     "setvl. 5,4,5,0,1,1",
  86                         ]
  87         self._do_tst(expected)
  88
  89     def test_6_sv_setvl(self):
  90         expected = [
  91                     "sv.setvl 5,4,5,0,1,1",
  92                     "sv.setvl 63,35,5,0,1,1",
  93                         ]
  94         self._do_tst(expected)
  95
  96     def test_7_batch(self):
  97         "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
  98         expected = [
  99                     "addi 2,2,0",
 100                     "addis 9,2,0",
 101                     "addi 9,9,0",
 102                     "rlwinm 7,7,2,0,29",
 103                     "mulli 0,7,31",
 104                     "add 10,6,0",
 105                     "setvl 0,0,8,1,1,0",
 106                     "addi 16,4,124",
 107                     "lfiwax 0,0,5",
 108                     "addi 5,3,64",
 109                     "sv.lfs *32,256(4)",
 110                     "sv.lfs *40,256(5)",
 111                     "sv.fmuls *32,*32,*40",
 112                     "sv.fadds 0,*32,0",
 113                     "addi 5,3,192",
 114                     "addi 4,4,128",
 115                     "sv.lfs *32,256(4)",
 116                     "sv.lfs *40,256(5)",
 117                     "sv.fmuls *32,*32,*40",
 118                     "sv.fsubs 0,0,*32",
 119                     "addi 4,4,-128",
 120                     "stfs 0,0(6)",
 121                     "add 6,6,7",
 122                     "addi 4,4,4",
 123                     "addi 0,0,15",
 124                     "mtspr 288,0",
 125                     "addi 8,0,4",
 126                     "lfiwax 0,0,9",
 127                     "lfiwax 1,0,9",
 128                     "addi 5,3,64",
 129                     "add 5,5,8",
 130                     "sv.lfs *32,256(5)",
 131                     "sv.lfs *40,256(4)",
 132                     "sv.lfs *48,256(16)",
 133                     "sv.fmuls *40,*32,*40",
 134                     "sv.fadds 0,0,*40",
 135                     "sv.fmuls *32,*32,*48",
 136                     "sv.fsubs 1,1,*32",
 137                     "addi 5,3,192",
 138                     "subf 5,8,5",
 139                     "addi 4,4,128",
 140                     "addi 16,16,128",
 141                     "sv.lfs *32,256(5)",
 142                     "sv.lfs *40,256(4)",
 143                     "sv.lfs *48,256(16)",
 144                     "sv.fmuls *40,*32,*40",
 145                     "sv.fsubs 0,0,*40",
 146                     "sv.fmuls *32,*32,*48",
 147                     "sv.fsubs 1,1,*32",
 148                     "addi 4,4,-128",
 149                     "addi 16,16,-128",
 150                     "stfs 0,0(6)",
 151                     "add 6,6,7",
 152                     "stfs 1,0(10)",
 153                     "subf 10,7,10",
 154                     "addi 8,8,4",
 155                     "addi 4,4,4",
 156                     "addi 16,16,-4",
 157                     "bc 16,0,-0xb4",
 158                     "addi 5,3,128",
 159                     "addi 4,4,128",
 160                     "lfiwax 0,0,9",
 161                     "sv.lfs *32,256(4)",
 162                     "sv.lfs *40,256(5)",
 163                     "sv.fmuls *32,*32,*40",
 164                     "sv.fsubs 0,0,*32",
 165                     "stfs 0,0(6)",
 166                     "bclr 20,0,0",
 167                         ]
 168         self._do_tst(expected)
 169
 170     def test_8_madd(self):
 171         expected = [
 172                     "maddhd 5,4,5,3",
 173                     "maddhdu 5,4,5,3",
 174                     "maddld 5,4,5,3",
 175                         ]
 176         self._do_tst(expected)
 177
 178     def test_9_fptrans(self):
 179         "enumerates a list of fptrans instruction disassembly entries"
 180         db = Database(find_wiki_dir())
 181         entries = sorted(sv_binutils_fptrans.collect(db))
 182         dis = lambda entry: sv_binutils_fptrans.dis(entry, binutils=False)
 183         lst = []
 184         for generator in map(dis, entries):
 185             for line in generator:
 186                 lst.append(line)
 187         self._do_tst(lst)
 188
 189     def test_10_vec(self):
 190         expected = [
 191                     "sv.add./vec2 *3,*7,*11",
 192                     "sv.add./vec3 *3,*7,*11",
 193                     "sv.add./vec4 *3,*7,*11",
 194                         ]
 195         self._do_tst(expected)
 196
 197     def test_11_elwidth(self):
 198         expected = [
 199                     "sv.add./dw=8 *3,*7,*11",
 200                     "sv.add./dw=16 *3,*7,*11",
 201                     "sv.add./dw=32 *3,*7,*11",
 202                     "sv.add./sw=8 *3,*7,*11",
 203                     "sv.add./sw=16 *3,*7,*11",
 204                     "sv.add./sw=32 *3,*7,*11",
 205                     "sv.add./dw=8/sw=16 *3,*7,*11",
 206                     "sv.add./dw=16/sw=32 *3,*7,*11",
 207                     "sv.add./dw=32/sw=8 *3,*7,*11",
 208                     "sv.add./w=32 *3,*7,*11",
 209                     "sv.add./w=8 *3,*7,*11",
 210                     "sv.add./w=16 *3,*7,*11",
 211                         ]
 212         self._do_tst(expected)
 213
 214     def test_12_sat(self):
 215         expected = [
 216                     "sv.add./satu *3,*7,*11",
 217                     "sv.add./sats *3,*7,*11",
 218                         ]
 219         self._do_tst(expected)
 220
 221     def test_12_mr_r(self):
 222         expected = [
 223                     "sv.add./mrr/vec2 *3,*7,*11",
 224                     "sv.add./mr/vec2 *3,*7,*11",
 225                     "sv.add./mrr *3,*7,*11",
 226                     "sv.add./mr *3,*7,*11",
 227                         ]
 228         self._do_tst(expected)
 229
 230     def test_13_RC1(self):
 231         expected = [
 232                     "sv.add/ff=RC1 *3,*7,*11",
 233                     "sv.add/ff=~RC1 *3,*7,*11",
 234                         ]
 235         self._do_tst(expected)
 236
 237     def test_14_rc1_ff_pr(self):
 238         expected = [
 239                     "sv.add./ff=eq *3,*7,*11",
 240                     "sv.add./ff=ns *3,*7,*11",
 241                     "sv.add./ff=lt *3,*7,*11",
 242                     "sv.add./ff=ge *3,*7,*11",
 243                     "sv.add./ff=le *3,*7,*11",
 244                     "sv.add./ff=gt *3,*7,*11",
 245                     "sv.add./ff=ne *3,*7,*11",
 246                         ]
 247         self._do_tst(expected)
 248
 249     def test_15_predicates(self):
 250         expected = [
 251                     "sv.add./m=r3 *3,*7,*11",
 252                     "sv.add./m=1<<r3 *3,*7,*11",
 253                     "sv.add./m=~r10 *3,*7,*11",
 254                     "sv.add./m=so *3,*7,*11",
 255                     "sv.add./m=ne *3,*7,*11",
 256                     "sv.add./m=lt *3,*7,*11",
 257                     "sv.add. *3,*7,*11",
 258                     "sv.extsw/m=r30 3,7",
 259                     "sv.extsw/dm=~r30/sm=r30 3,7",
 260                     "sv.extsw/dm=eq/sm=gt 3,7",
 261                     "sv.extsw/sm=~r3 3,7",
 262                     "sv.extsw/dm=r30 3,7",
 263                         ]
 264         self._do_tst(expected)
 265
 266     def test_15_els(self):
 267         expected = [
 268                     "sv.stw/els *4,16(2)",
 269                     "sv.lfs/els *1,256(4)",
 270                         ]
 271         self._do_tst(expected)
 272
 273     def test_16_bc(self):
 274         """bigger list in test_pysvp64dis_branch.py, this one's "quick"
 275         """
 276         expected = [
 277                     "sv.bc/all 12,*1,0xc",
 278                     "sv.bc/snz 12,*1,0xc",
 279                     "sv.bc/m=r3/snz 12,*1,0xc",
 280                     "sv.bc/m=r3/sz 12,*1,0xc",
 281                     "sv.bc/all/sl/slu 12,*1,0xc",
 282                     "sv.bc/all/lru/sl/slu/snz 12,*1,0xc",
 283                     "sv.bc/all/lru/sl/slu/snz/vs 12,*1,0xc",
 284                     "sv.bc/all/lru/sl/slu/snz/vsi 12,*1,0xc",
 285                     "sv.bc/all/lru/sl/slu/snz/vsb 12,*1,0xc",
 286                     "sv.bc/all/lru/sl/slu/snz/vsbi 12,*1,0xc",
 287                     "sv.bc/all/ctr/lru/sl/slu/snz 12,*1,0xc",
 288                     "sv.bc/all/cti/lru/sl/slu/snz 12,*1,0xc",
 289                     "sv.bc/all/ctr/lru/sl/slu/snz/vsb 12,*1,0xc",
 290                         ]
 291         self._do_tst(expected)
 292
 293     def test_17_vli(self):
 294         expected = [
 295                     "sv.add/ff=RC1/vli 3,7,11",
 296                     "sv.add/ff=~RC1/vli 3,7,11",
 297                         ]
 298         self._do_tst(expected)
 299
 300     def test_18_sea(self):
 301         expected = [
 302                     "sv.ldux/sea 5,6,7",
 303                     "sv.ldux/pi/sea 5,6,7",
 304                         ]
 305         self._do_tst(expected)
 306
 307     def test_19_ldst_idx_els(self):
 308         expected = [
 309                     "sv.stdx/els *4,16,2",
 310                     "sv.stdx/els/sea *4,16,2",
 311                     "sv.ldx/els *4,16,2",
 312                     "sv.ldx/els/sea *4,16,2",
 313                         ]
 314         self._do_tst(expected)
 315
 316     def test_20_cmp(self):
 317         expected = [
 318                     "sv.cmp *4,1,*0,1",
 319                     "sv.cmp/ff=eq *4,1,*0,1",
 320                     "sv.cmp/ff=eq/vli *4,1,*0,1",
 321                     "sv.cmp/ff=ne *4,1,*0,1",
 322                     "sv.cmp/ff=eq/m=r3/zz *4,1,*0,1",
 323                     "sv.cmp/ff=lt/m=r3/zz *4,1,*0,1",
 324                     "sv.cmp/ff=gt/m=r3/zz *4,1,*0,1",
 325                     "sv.cmp/zz/ff=gt/m=r3 *4,1,*0,1", # WRONG
 326                         ]
 327         self._do_tst(expected)
 328
 329     def test_21_addex(self):
 330         expected = [
 331                     "addex 5,3,2,0",
 332                     "sv.addex 5,3,2,0",
 333                     "sv.addex *5,3,2,0",
 334                         ]
 335         self._do_tst(expected)
 336
 337     def test_22_ld(self):
 338         expected = [
 339                     "ld 4,0(5)",
 340                     "ld 4,16(5)",       # sigh, needs magic-shift (D||0b00)
 341                     "sv.ld 4,16(5)",    # ditto
 342                         ]
 343         self._do_tst(expected)
 344
 345     def test_23_lq(self):
 346         expected = [
 347                     "lq 4,0(5)",
 348                     "lq 4,16(5)",      # ditto, magic-shift (DQ||0b0000)
 349                     "lq 4,32(5)",      # ditto
 350                     "sv.lq 4,16(5)",   # ditto
 351                         ]
 352         self._do_tst(expected)
 353
 354     def test_24_bc(self):
 355         expected = [
 356                     "b 0x28",
 357                     "bc 16,0,-0xb4",
 358                         ]
 359         self._do_tst(expected)
 360
 361     def test_25_stq(self):
 362         expected = [
 363                     "stq 4,0(5)",
 364                     "stq 4,8(5)",
 365                     "stq 4,16(5)",
 366                     "sv.stq 4,16(*5)",
 367                         ]
 368         self._do_tst(expected)
 369
 370     def test_26_sv_stq_vector_name(self):
 371         expected = [
 372                     "sv.stq *4,16(*5)", # RSp not recognised as "vector" name
 373                         ]
 374         self._do_tst(expected)
 375
 376     def test_27_sc(self):
 377         expected = [
 378                     "sc 0",
 379                     "sc 1",
 380                     "scv 1",
 381                     "scv 2",
 382                         ]
 383         self._do_tst(expected)
 384
 385     def test_28_rfid(self):
 386         expected = [
 387                     "rfid",
 388                     "rfscv",
 389                         ]
 390         self._do_tst(expected)
 391
 392     def test_29_postinc(self):
 393         expected = [
 394                     "sv.ldu/pi 5,8(2)",
 395                     "sv.lwzu/pi *6,8(2)",
 396                     "sv.lwzu/pi *6,24(2)",
 397                     "sv.stwu/pi *6,24(2)",
 398                         ]
 399         self._do_tst(expected)
 400
 401     def test_29_dsld_dsrd(self):
 402         expected = [
 403                     "dsld 5,4,5,3",
 404                     "dsrd 5,4,5,3",
 405                     "dsld. 5,4,5,3",
 406                     "dsrd. 5,4,5,3",
 407                     "sv.dsld *6,4,5,3",
 408                     "sv.dsrd *6,4,5,3",
 409                     "sv.dsld. *6,4,5,3",
 410                     "sv.dsrd. *6,4,5,3",
 411                         ]
 412         self._do_tst(expected)
 413
 414     def test_30_divmod2du(self):
 415         expected = [
 416                     "divmod2du 5,4,5,3",
 417                     "maddedu 5,4,5,3",
 418                     "sv.divmod2du 5,4,5,3",
 419                     "sv.divmod2du *6,4,*0,3",
 420                     "sv.maddedu 5,4,5,3",
 421                     "sv.maddedu *6,4,5,3",
 422                         ]
 423         self._do_tst(expected)
 424
 425     def test_31_sadd_saddw_sadduw(self):
 426         expected = [
 427                     "sadd 31,0,0,0",
 428                     "sadd 0,31,0,0",
 429                     "sadd 0,0,31,0",
 430                     "sadd 0,0,0,3",
 431                     "sadd. 31,0,0,0",
 432                     "sadd. 0,31,0,0",
 433                     "sadd. 0,0,31,0",
 434                     "sadd. 0,0,0,3",
 435                     "saddw 31,0,0,0",
 436                     "saddw 0,31,0,0",
 437                     "saddw 0,0,31,0",
 438                     "saddw 0,0,0,3",
 439                     "saddw. 31,0,0,0",
 440                     "saddw. 0,31,0,0",
 441                     "saddw. 0,0,31,0",
 442                     "saddw. 0,0,0,3",
 443                     "sadduw 31,0,0,0",
 444                     "sadduw 0,31,0,0",
 445                     "sadduw 0,0,31,0",
 446                     "sadduw 0,0,0,3",
 447                     "sadduw. 31,0,0,0",
 448                     "sadduw. 0,31,0,0",
 449                     "sadduw. 0,0,31,0",
 450                     "sadduw. 0,0,0,3",
 451                         ]
 452         self._do_tst(expected)
 453
 454     def test_32_ldst_idx_ffirst(self):
 455         expected = [
 456                     "sv.stdx/ff=RC1 *4,16,2",
 457                     "sv.stdx/ff=~RC1 *4,16,2",
 458                     "sv.ldx/ff=RC1 *4,16,2",
 459                     "sv.ldx/ff=~RC1 *4,16,2",
 460                         ]
 461         self._do_tst(expected)
 462
 463     def test_33_ldst_imm_ffirst(self):
 464         expected = [
 465                     "sv.std/ff=RC1 *4,16(2)",
 466                     "sv.std/ff=~RC1 *4,16(2)",
 467                     "sv.ld/ff=RC1 *4,16(2)",
 468                     "sv.ld/ff=~RC1 *4,16(2)",
 469                         ]
 470         self._do_tst(expected)
 471
 472     def test_34_ldst_update_imm_ffirst(self):
 473         expected = [
 474                     "sv.ldu/ff=~RC1/vli *16,0(*17)",
 475                         ]
 476         self._do_tst(expected)
 477
 478     def test_35_ffmadds(self):
 479         expected = [
 480                     "sv.ffmadds *0,*0,*0",
 481                         ]
 482         self._do_tst(expected)
 483
 484     def test_36_extras_rlwimi(self):
 485         self._do_tst(["sv.rlwimi 3,1,5,20,6"])
 486
 487     def test_36_extras_rlwimi_(self):
 488         self._do_tst(["sv.rlwimi. 3,1,5,20,6"])
 489
 490     def test_36_extras_rldimi(self):
 491         self._do_tst(["sv.rldimi 3,4,56,4"])
 492
 493     def test_36_extras_rldimi_(self):
 494         self._do_tst(["sv.rldimi. 3,4,56,4"])
 495
 496     def test_36_extras_fishmv(self):
 497         self._do_tst(["sv.fishmv 3,4048"]) # 0x0FD0
 498
 499     def test_37_extras_rldimi(self):
 500         self._do_tst(["rldimi 3,4,56,4"])
 501
 502 if __name__ == "__main__":
 503     unittest.main()