src/openpower/sv/trans/test_pysvp64dis.py

   1 from openpower.simulator.program import Program
   2 from openpower.sv.trans.pysvp64dis import load, dump
   3 from openpower.sv.trans.svp64 import SVP64Asm
   4 from openpower.decoder.power_insn import Database, Verbosity
   5 from openpower.decoder.power_enums import find_wiki_dir
   6 from openpower.sv import sv_binutils_fptrans
   7 import unittest
   8 import itertools
   9 import sys
  10
  11 class SVSTATETestCase(unittest.TestCase):
  12
  13     def _do_tst(self, expected):
  14         isa = SVP64Asm(expected)
  15         lst = list(isa)
  16         with Program(lst, bigendian=False) as program:
  17             print ("ops", program._instructions)
  18             program.binfile.seek(0)
  19             insns = load(program.binfile)
  20             #for insn in insns:
  21                 #print ("insn", insn)
  22             insns = list(insns)
  23             print ("insns", insns)
  24             for i, line in enumerate(dump(insns, verbosity=Verbosity.SHORT)):
  25                 name = expected[i].split(" ")[0]
  26                 with self.subTest("%d:%s" % (i, name)):
  27                     print("instruction", repr(line), repr(expected[i]))
  28                     self.assertEqual(expected[i], line,
  29                                      "instruction does not match "
  30                                      "'%s' expected '%s'" % (line, expected[i]))
  31
  32
  33     def tst_0_add(self):
  34         expected = ['addi 1,5,2',
  35                     'add 1,5,2',
  36                     'add. 1,5,2',
  37                     'addo 1,5,2',
  38                     'addo. 1,5,2',
  39                         ]
  40         self._do_tst(expected)
  41
  42     def tst_1_svshape2(self):
  43         expected = [
  44                     'svshape2 12,1,15,5,0,0'
  45                         ]
  46         self._do_tst(expected)
  47
  48     def tst_2_d_custom_op(self):
  49         expected = [
  50                     'fishmv 12,2',
  51                     'fmvis 12,97',
  52                     'addpcis 12,5',
  53                         ]
  54         self._do_tst(expected)
  55
  56     def tst_3_sv_isel(self):
  57         expected = [
  58                     'sv.isel 12,2,3,33',
  59                     'sv.isel 12,2,3,*33',
  60                     'sv.isel 12,2,3,*483',
  61                     'sv.isel 12,2,3,63',
  62                     'sv.isel 12,2,3,*99',
  63                         ]
  64         self._do_tst(expected)
  65
  66     def tst_4_sv_crand(self):
  67         expected = [
  68                     'sv.crand *16,*2,*33',
  69                     'sv.crand 12,2,33',
  70                     'sv.crand/ff=eq/m=r10 12,2,33',
  71                     'sv.crand/m=r10 12,2,33',
  72                     'sv.crand/m=r10/sz 12,2,33',
  73                     # XXX dz/sz is not the canonical way, must be zz
  74                     'sv.crand/dz/m=r10/sz 12,2,33', # NOT OK
  75                     'sv.crand/m=r10/zz 12,2,33',    # SHOULD PASS
  76                         ]
  77         self._do_tst(expected)
  78
  79     def tst_5_setvl(self):
  80         expected = [
  81                     "setvl 5,4,5,0,1,1",
  82                     "setvl. 5,4,5,0,1,1",
  83                         ]
  84         self._do_tst(expected)
  85
  86     def tst_6_sv_setvl(self):
  87         expected = [
  88                     "sv.setvl 5,4,5,0,1,1",
  89                     "sv.setvl 63,35,5,0,1,1",
  90                         ]
  91         self._do_tst(expected)
  92
  93     def tst_7_batch(self):
  94         "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
  95         expected = [
  96                     "addi 2,2,0",
  97                     "addis 9,2,0",
  98                     "addi 9,9,0",
  99                     "rlwinm 7,7,2,0,29",
 100                     "mulli 0,7,31",
 101                     "add 10,6,0",
 102                     "setvl 0,0,8,1,1,0",
 103                     "addi 16,4,124",
 104                     "lfiwax 0,0,5",
 105                     "addi 5,3,64",
 106                     "sv.lfs *32,256(4)",
 107                     "sv.lfs *40,256(5)",
 108                     "sv.fmuls *32,*32,*40",
 109                     "sv.fadds 0,*32,0",
 110                     "addi 5,3,192",
 111                     "addi 4,4,128",
 112                     "sv.lfs *32,256(4)",
 113                     "sv.lfs *40,256(5)",
 114                     "sv.fmuls *32,*32,*40",
 115                     "sv.fsubs 0,0,*32",
 116                     "addi 4,4,-128",
 117                     "stfs 0,0(6)",
 118                     "add 6,6,7",
 119                     "addi 4,4,4",
 120                     "addi 0,0,15",
 121                     "mtspr 288,0",
 122                     "addi 8,0,4",
 123                     "lfiwax 0,0,9",
 124                     "lfiwax 1,0,9",
 125                     "addi 5,3,64",
 126                     "add 5,5,8",
 127                     "sv.lfs *32,256(5)",
 128                     "sv.lfs *40,256(4)",
 129                     "sv.lfs *48,256(16)",
 130                     "sv.fmuls *40,*32,*40",
 131                     "sv.fadds 0,0,*40",
 132                     "sv.fmuls *32,*32,*48",
 133                     "sv.fsubs 1,1,*32",
 134                     "addi 5,3,192",
 135                     "subf 5,8,5",
 136                     "addi 4,4,128",
 137                     "addi 16,16,128",
 138                     "sv.lfs *32,256(5)",
 139                     "sv.lfs *40,256(4)",
 140                     "sv.lfs *48,256(16)",
 141                     "sv.fmuls *40,*32,*40",
 142                     "sv.fsubs 0,0,*40",
 143                     "sv.fmuls *32,*32,*48",
 144                     "sv.fsubs 1,1,*32",
 145                     "addi 4,4,-128",
 146                     "addi 16,16,-128",
 147                     "stfs 0,0(6)",
 148                     "add 6,6,7",
 149                     "stfs 1,0(10)",
 150                     "subf 10,7,10",
 151                     "addi 8,8,4",
 152                     "addi 4,4,4",
 153                     "addi 16,16,-4",
 154                     "bc 16,0,-0xb4",
 155                     "addi 5,3,128",
 156                     "addi 4,4,128",
 157                     "lfiwax 0,0,9",
 158                     "sv.lfs *32,256(4)",
 159                     "sv.lfs *40,256(5)",
 160                     "sv.fmuls *32,*32,*40",
 161                     "sv.fsubs 0,0,*32",
 162                     "stfs 0,0(6)",
 163                     "bclr 20,0,0",
 164                         ]
 165         self._do_tst(expected)
 166
 167     def tst_8_madd(self):
 168         expected = [
 169                     "maddhd 5,4,5,3",
 170                     "maddhdu 5,4,5,3",
 171                     "maddld 5,4,5,3",
 172                         ]
 173         self._do_tst(expected)
 174
 175     def tst_9_fptrans(self):
 176         "enumerates a list of fptrans instruction disassembly entries"
 177         db = Database(find_wiki_dir())
 178         entries = sorted(sv_binutils_fptrans.collect(db))
 179         dis = lambda entry: sv_binutils_fptrans.dis(entry, binutils=False)
 180         self._do_tst(list(map(dis, entries)))
 181
 182     def tst_10_vec(self):
 183         expected = [
 184                     "sv.add./vec2 *3,*7,*11",
 185                     "sv.add./vec3 *3,*7,*11",
 186                     "sv.add./vec4 *3,*7,*11",
 187                         ]
 188         self._do_tst(expected)
 189
 190     def tst_11_elwidth(self):
 191         expected = [
 192                     "sv.add./dw=8 *3,*7,*11",
 193                     "sv.add./dw=16 *3,*7,*11",
 194                     "sv.add./dw=32 *3,*7,*11",
 195                     "sv.add./sw=8 *3,*7,*11",
 196                     "sv.add./sw=16 *3,*7,*11",
 197                     "sv.add./sw=32 *3,*7,*11",
 198                     "sv.add./dw=8/sw=16 *3,*7,*11",
 199                     "sv.add./dw=16/sw=32 *3,*7,*11",
 200                     "sv.add./dw=32/sw=8 *3,*7,*11",
 201                     "sv.add./w=32 *3,*7,*11",
 202                     "sv.add./w=8 *3,*7,*11",
 203                     "sv.add./w=16 *3,*7,*11",
 204                         ]
 205         self._do_tst(expected)
 206
 207     def tst_12_sat(self):
 208         expected = [
 209                     "sv.add./satu *3,*7,*11",
 210                     "sv.add./sats *3,*7,*11",
 211                         ]
 212         self._do_tst(expected)
 213
 214     def tst_12_mr_r(self):
 215         expected = [
 216                     "sv.add./mrr/vec2 *3,*7,*11",
 217                     "sv.add./mr/vec2 *3,*7,*11",
 218                     "sv.add./mrr *3,*7,*11",
 219                     "sv.add./mr *3,*7,*11",
 220                         ]
 221         self._do_tst(expected)
 222
 223     def tst_13_RC1(self):
 224         expected = [
 225                     "sv.add/ff=RC1 *3,*7,*11",
 226                     "sv.add/pr=RC1 *3,*7,*11",
 227                     "sv.add/ff=~RC1 *3,*7,*11",
 228                     "sv.add/pr=~RC1 *3,*7,*11",
 229                         ]
 230         self._do_tst(expected)
 231
 232     def tst_14_rc1_ff_pr(self):
 233         expected = [
 234                     "sv.add./ff=eq *3,*7,*11",
 235                     "sv.add./ff=ns *3,*7,*11",
 236                     "sv.add./ff=lt *3,*7,*11",
 237                     "sv.add./ff=ge *3,*7,*11",
 238                     "sv.add./ff=le *3,*7,*11",
 239                     "sv.add./ff=gt *3,*7,*11",
 240                     "sv.add./ff=ne *3,*7,*11",
 241                     "sv.add./pr=eq *3,*7,*11",
 242                     "sv.add./pr=ns *3,*7,*11",
 243                         ]
 244         self._do_tst(expected)
 245
 246     def tst_15_predicates(self):
 247         expected = [
 248                     "sv.add./m=r3 *3,*7,*11",
 249                     "sv.add./m=1<<r3 *3,*7,*11",
 250                     "sv.add./m=~r10 *3,*7,*11",
 251                     "sv.add./m=so *3,*7,*11",
 252                     "sv.add./m=ne *3,*7,*11",
 253                     "sv.add./m=lt *3,*7,*11",
 254                     "sv.add. *3,*7,*11",
 255                     "sv.extsw/m=r30 3,7",
 256                     "sv.extsw/dm=~r30/sm=r30 3,7",
 257                     "sv.extsw/dm=eq/sm=gt 3,7",
 258                     "sv.extsw/sm=~r3 3,7",
 259                     "sv.extsw/dm=r30 3,7",
 260                         ]
 261         self._do_tst(expected)
 262
 263     def tst_15_els(self):
 264         expected = [
 265                     "sv.stw/els *4,16(2)",
 266                     "sv.lfs/els *1,256(4)",
 267                         ]
 268         self._do_tst(expected)
 269
 270     def tst_16_bc(self):
 271         """bigger list in test_pysvp64dis_branch.py, this one's "quick"
 272         """
 273         expected = [
 274                     "sv.bc/all 12,*1,0xc",
 275                     "sv.bc/snz 12,*1,0xc",
 276                     "sv.bc/m=r3/snz 12,*1,0xc",
 277                     "sv.bc/m=r3/sz 12,*1,0xc",
 278                     "sv.bc/all/sl/slu 12,*1,0xc",
 279                     "sv.bc/all/lru/sl/slu/snz 12,*1,0xc",
 280                     "sv.bc/all/lru/sl/slu/snz/vs 12,*1,0xc",
 281                     "sv.bc/all/lru/sl/slu/snz/vsi 12,*1,0xc",
 282                     "sv.bc/all/lru/sl/slu/snz/vsb 12,*1,0xc",
 283                     "sv.bc/all/lru/sl/slu/snz/vsbi 12,*1,0xc",
 284                     "sv.bc/all/ctr/lru/sl/slu/snz 12,*1,0xc",
 285                     "sv.bc/all/cti/lru/sl/slu/snz 12,*1,0xc",
 286                     "sv.bc/all/ctr/lru/sl/slu/snz/vsb 12,*1,0xc",
 287                         ]
 288         self._do_tst(expected)
 289
 290     def tst_17_vli(self):
 291         expected = [
 292                     "sv.add/ff=RC1/vli 3,7,11",
 293                     "sv.add/ff=~RC1/vli 3,7,11",
 294                         ]
 295         self._do_tst(expected)
 296
 297     def tst_18_sea(self):
 298         expected = [
 299                     "sv.ldux/sea 5,6,7",
 300                         ]
 301         self._do_tst(expected)
 302
 303     def tst_19_ldst_idx_els(self):
 304         expected = [
 305                     "sv.stdx/els *4,16,2",
 306                     "sv.stdx/els/sea *4,16,2",
 307                     "sv.ldx/els *4,16,2",
 308                     "sv.ldx/els/sea *4,16,2",
 309                         ]
 310         self._do_tst(expected)
 311
 312     def tst_20_cmp(self):
 313         expected = [
 314                     "sv.cmp *4,1,*0,1",
 315                     "sv.cmp/ff=RC1 *4,1,*0,1",
 316                     "sv.cmp/ff=RC1/vli *4,1,*0,1",
 317                     "sv.cmp/ff=~RC1 *4,1,*0,1",
 318                     "sv.cmp/ff=RC1/m=r3/sz *4,1,*0,1",
 319                     "sv.cmp/dz/ff=RC1/m=r3 *4,1,*0,1",
 320                     "sv.cmp/dz/ff=RC1/m=r3/sz *4,1,*0,1",
 321                         ]
 322         self._do_tst(expected)
 323
 324     def tst_21_addex(self):
 325         expected = [
 326                     "addex 5,3,2,0",
 327                     "sv.addex 5,3,2,0",
 328                     "sv.addex *5,3,2,0",
 329                         ]
 330         self._do_tst(expected)
 331
 332     def tst_22_ld(self):
 333         expected = [
 334                     "ld 4,0(5)",
 335                     "ld 4,16(5)",       # sigh, needs magic-shift (D||0b00)
 336                     "sv.ld 4,16(5)",    # ditto
 337                         ]
 338         self._do_tst(expected)
 339
 340     def tst_23_lq(self):
 341         expected = [
 342                     "lq 4,0(5)",
 343                     "lq 4,16(5)",      # ditto, magic-shift (DQ||0b0000)
 344                     "lq 4,32(5)",      # ditto
 345                     "sv.lq 4,16(5)",   # ditto
 346                         ]
 347         self._do_tst(expected)
 348
 349     def tst_24_bc(self):
 350         expected = [
 351                     "b 0x28",
 352                     "bc 16,0,-0xb4",
 353                         ]
 354         self._do_tst(expected)
 355
 356     def tst_25_stq(self):
 357         expected = [
 358                     "stq 4,0(5)",
 359                     "stq 4,8(5)",
 360                     "stq 4,16(5)",
 361                     "sv.stq 4,16(*5)",
 362                         ]
 363         self._do_tst(expected)
 364
 365     def tst_26_sv_stq_vector_name(self):
 366         expected = [
 367                     "sv.stq *4,16(*5)", # RSp not recognised as "vector" name
 368                         ]
 369         self._do_tst(expected)
 370
 371     def test_27_sc(self):
 372         expected = [
 373                     #"sc 0",
 374                     #"sc 1",
 375                     #"scv 1",
 376                     #"scv 2",
 377                     "attn",
 378                         ]
 379         self._do_tst(expected)
 380
 381
 382 if __name__ == "__main__":
 383     unittest.main()