src/openpower/test/alu/alu_cases.py

   1 import random
   2 from openpower.test.common import TestAccumulatorBase
   3 from openpower.endian import bigendian
   4 from openpower.simulator.program import Program
   5 from openpower.decoder.selectable_int import SelectableInt
   6 from openpower.decoder.power_enums import XER_bits
   7 from openpower.decoder.isa.caller import special_sprs
   8 from openpower.test.state import ExpectedState
   9 import unittest
  10
  11
  12 class ALUTestCase(TestAccumulatorBase):
  13
  14     def case_1_regression(self):
  15         lst = [f"add. 3, 1, 2"]
  16         initial_regs = [0] * 32
  17         initial_regs[1] = 0xc523e996a8ff6215
  18         initial_regs[2] = 0xe1e5b9cc9864c4a8
  19         e = ExpectedState(pc=4)
  20         e.intregs[1] = 0xc523e996a8ff6215
  21         e.intregs[2] = 0xe1e5b9cc9864c4a8
  22         e.intregs[3] = 0xa709a363416426bd
  23         e.crregs[0] = 0x8
  24         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  25
  26     def case_2_regression(self):
  27         lst = [f"extsw 3, 1"]
  28         initial_regs = [0] * 32
  29         initial_regs[1] = 0xb6a1fc6c8576af91
  30         e = ExpectedState(pc=4)
  31         e.intregs[1] = 0xb6a1fc6c8576af91
  32         e.intregs[3] = 0xffffffff8576af91
  33         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  34
  35         lst = [f"subf 3, 1, 2"]
  36         initial_regs = [0] * 32
  37         initial_regs[1] = 0x3d7f3f7ca24bac7b
  38         initial_regs[2] = 0xf6b2ac5e13ee15c2
  39         e = ExpectedState(pc=4)
  40         e.intregs[1] = 0x3d7f3f7ca24bac7b
  41         e.intregs[2] = 0xf6b2ac5e13ee15c2
  42         e.intregs[3] = 0xb9336ce171a26947
  43         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  44
  45         lst = [f"subf 3, 1, 2"]
  46         initial_regs = [0] * 32
  47         initial_regs[1] = 0x833652d96c7c0058
  48         initial_regs[2] = 0x1c27ecff8a086c1a
  49         e = ExpectedState(pc=4)
  50         e.intregs[1] = 0x833652d96c7c0058
  51         e.intregs[2] = 0x1c27ecff8a086c1a
  52         e.intregs[3] = 0x98f19a261d8c6bc2
  53         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  54
  55         lst = [f"extsb 3, 1"]
  56         initial_regs = [0] * 32
  57         initial_regs[1] = 0x7f9497aaff900ea0
  58         e = ExpectedState(pc=4)
  59         e.intregs[1] = 0x7f9497aaff900ea0
  60         e.intregs[3] = 0xffffffffffffffa0
  61         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  62
  63         lst = [f"add 3, 1, 2"]
  64         initial_regs = [0] * 32
  65         initial_regs[1] = 0x2e08ae202742baf8
  66         initial_regs[2] = 0x86c43ece9efe5baa
  67         e = ExpectedState(pc=4)
  68         e.intregs[1] = 0x2e08ae202742baf8
  69         e.intregs[2] = 0x86c43ece9efe5baa
  70         e.intregs[3] = 0xb4cceceec64116a2
  71         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  72
  73     def case_rand(self):
  74         insns = ["add", "add.", "subf"]
  75         for i in range(40):
  76             choice = random.choice(insns)
  77             lst = [f"{choice} 3, 1, 2"]
  78             initial_regs = [0] * 32
  79             initial_regs[1] = random.randint(0, (1 << 64)-1)
  80             initial_regs[2] = random.randint(0, (1 << 64)-1)
  81             self.add_case(Program(lst, bigendian), initial_regs)
  82
  83     def case_addme_ca_0(self):
  84         insns = ["addme", "addme.", "addmeo", "addmeo."]
  85         for choice in insns:
  86             lst = [f"{choice} 6, 16"]
  87             for value in [0x7ffffffff,
  88                           0xffff80000]:
  89                 initial_regs = [0] * 32
  90                 initial_regs[16] = value
  91                 initial_sprs = {}
  92                 xer = SelectableInt(0, 64)
  93                 xer[XER_bits['CA']] = 0  # input carry is 0 (see test below)
  94                 initial_sprs[special_sprs['XER']] = xer
  95
  96                 # create expected results.  pc should be 4 (one instruction)
  97                 e = ExpectedState(pc=4)
  98                 # input value should not be modified
  99                 e.intregs[16] = value
 100                 # carry-out should always occur
 101                 e.ca = 0x3
 102                 # create output value
 103                 if value == 0x7ffffffff:
 104                     e.intregs[6] = 0x7fffffffe
 105                 else:
 106                     e.intregs[6] = 0xffff7ffff
 107                 # CR version needs an expected CR
 108                 if '.' in choice:
 109                     e.crregs[0] = 0x4
 110                 self.add_case(Program(lst, bigendian),
 111                               initial_regs, initial_sprs,
 112                               expected=e)
 113
 114     def case_addme_ca_1(self):
 115         insns = ["addme", "addme.", "addmeo", "addmeo."]
 116         for choice in insns:
 117             lst = [f"{choice} 6, 16"]
 118             for value in [0x7ffffffff, # fails, bug #476
 119                           0xffff80000]:
 120                 initial_regs = [0] * 32
 121                 initial_regs[16] = value
 122                 initial_sprs = {}
 123                 xer = SelectableInt(0, 64)
 124                 xer[XER_bits['CA']] = 1 # input carry is 1 (differs from above)
 125                 initial_sprs[special_sprs['XER']] = xer
 126                 self.add_case(Program(lst, bigendian),
 127                               initial_regs, initial_sprs)
 128
 129     def case_addme_ca_so_3(self):
 130         """bug where SO does not get passed through to CR0
 131         """
 132         lst = ["addme. 6, 16"]
 133         initial_regs = [0] * 32
 134         initial_regs[16] = 0x7ffffffff
 135         initial_sprs = {}
 136         xer = SelectableInt(0, 64)
 137         xer[XER_bits['CA']] = 1
 138         xer[XER_bits['SO']] = 1
 139         initial_sprs[special_sprs['XER']] = xer
 140         self.add_case(Program(lst, bigendian),
 141                       initial_regs, initial_sprs)
 142
 143     def case_addze(self):
 144         insns = ["addze", "addze.", "addzeo", "addzeo."]
 145         for choice in insns:
 146             lst = [f"{choice} 6, 16"]
 147             initial_regs = [0] * 32
 148             initial_regs[16] = 0x00ff00ff00ff0080
 149             if choice == "addze":
 150                 e = ExpectedState(pc=4)
 151                 e.intregs[6] = 0xff00ff00ff0080
 152                 e.intregs[16] = 0xff00ff00ff0080
 153                 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 154             else:
 155                 self.add_case(Program(lst, bigendian), initial_regs)
 156
 157     def case_addis_nonzero_r0_regression(self):
 158         lst = [f"addis 3, 0, 1"]
 159         print(lst)
 160         initial_regs = [0] * 32
 161         initial_regs[0] = 5
 162         e = ExpectedState(initial_regs, pc=4)
 163         e.intregs[3] = 0x10000
 164         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 165
 166     def case_addis_nonzero_r0(self):
 167         for i in range(10):
 168             imm = random.randint(-(1 << 15), (1 << 15)-1)
 169             lst = [f"addis 3, 0, {imm}"]
 170             print(lst)
 171             initial_regs = [0] * 32
 172             initial_regs[0] = random.randint(0, (1 << 64)-1)
 173             self.add_case(Program(lst, bigendian), initial_regs)
 174
 175     def case_rand_imm(self):
 176         insns = ["addi", "addis", "subfic"]
 177         for i in range(10):
 178             choice = random.choice(insns)
 179             imm = random.randint(-(1 << 15), (1 << 15)-1)
 180             lst = [f"{choice} 3, 1, {imm}"]
 181             print(lst)
 182             initial_regs = [0] * 32
 183             initial_regs[1] = random.randint(0, (1 << 64)-1)
 184             self.add_case(Program(lst, bigendian), initial_regs)
 185
 186     def case_0_adde(self):
 187         lst = ["adde. 5, 6, 7"]
 188         for i in range(10):
 189             initial_regs = [0] * 32
 190             initial_regs[6] = random.randint(0, (1 << 64)-1)
 191             initial_regs[7] = random.randint(0, (1 << 64)-1)
 192             initial_sprs = {}
 193             xer = SelectableInt(0, 64)
 194             xer[XER_bits['CA']] = 1
 195             initial_sprs[special_sprs['XER']] = xer
 196             self.add_case(Program(lst, bigendian),
 197                           initial_regs, initial_sprs)
 198
 199     def case_cmp(self):
 200         lst = ["subf. 1, 6, 7",
 201                "cmp cr2, 1, 6, 7"]
 202         initial_regs = [0] * 32
 203         initial_regs[6] = 0x10
 204         initial_regs[7] = 0x05
 205         self.add_case(Program(lst, bigendian), initial_regs, {})
 206
 207     def case_cmp2(self):
 208         lst = ["cmp cr2, 0, 2, 3"]
 209         initial_regs = [0] * 32
 210         initial_regs[2] = 0xffffffffaaaaaaaa
 211         initial_regs[3] = 0x00000000aaaaaaaa
 212         self.add_case(Program(lst, bigendian), initial_regs, {})
 213
 214         lst = ["cmp cr2, 0, 4, 5"]
 215         initial_regs = [0] * 32
 216         initial_regs[4] = 0x00000000aaaaaaaa
 217         initial_regs[5] = 0xffffffffaaaaaaaa
 218         self.add_case(Program(lst, bigendian), initial_regs, {})
 219
 220     def case_cmp3(self):
 221         lst = ["cmp cr2, 1, 2, 3"]
 222         initial_regs = [0] * 32
 223         initial_regs[2] = 0xffffffffaaaaaaaa
 224         initial_regs[3] = 0x00000000aaaaaaaa
 225         self.add_case(Program(lst, bigendian), initial_regs, {})
 226
 227         lst = ["cmp cr2, 1, 4, 5"]
 228         initial_regs = [0] * 32
 229         initial_regs[4] = 0x00000000aaaaaaaa
 230         initial_regs[5] = 0xffffffffaaaaaaaa
 231         self.add_case(Program(lst, bigendian), initial_regs, {})
 232
 233     def case_cmpl_microwatt_0(self):
 234         """microwatt 1.bin:
 235            115b8:   40 50 d1 7c     .long 0x7cd15040 # cmpl 6, 0, 17, 10
 236             register_file.vhdl: Reading GPR 11 000000000001C026
 237             register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
 238             cr_file.vhdl: Reading CR 35055050
 239             cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
 240         """
 241
 242         lst = ["cmpl 6, 0, 17, 10"]
 243         initial_regs = [0] * 32
 244         initial_regs[0x11] = 0x1c026
 245         initial_regs[0xa] =  0xFEDF3FFF0001C025
 246         XER = 0xe00c0000
 247         CR = 0x35055050
 248
 249         self.add_case(Program(lst, bigendian), initial_regs,
 250                                 initial_sprs = {'XER': XER},
 251                                 initial_cr = CR)
 252
 253     def case_cmpl_microwatt_0_disasm(self):
 254         """microwatt 1.bin: disassembled version
 255            115b8:   40 50 d1 7c     .long 0x7cd15040 # cmpl 6, 0, 17, 10
 256             register_file.vhdl: Reading GPR 11 000000000001C026
 257             register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
 258             cr_file.vhdl: Reading CR 35055050
 259             cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
 260         """
 261
 262         dis = ["cmpl 6, 0, 17, 10"]
 263         lst = bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
 264         initial_regs = [0] * 32
 265         initial_regs[0x11] = 0x1c026
 266         initial_regs[0xa] =  0xFEDF3FFF0001C025
 267         XER = 0xe00c0000
 268         CR = 0x35055050
 269
 270         p = Program(lst, bigendian)
 271         p.assembly = '\n'.join(dis)+'\n'
 272         self.add_case(p, initial_regs,
 273                                 initial_sprs = {'XER': XER},
 274                                 initial_cr = CR)
 275
 276     def case_cmplw_microwatt_1(self):
 277         """microwatt 1.bin:
 278            10d94:   40 20 96 7c     cmplw   cr1,r22,r4
 279             gpr: 00000000ffff6dc1 <- r4
 280             gpr: 0000000000000000 <- r22
 281         """
 282
 283         lst = ["cmpl 1, 0, 22, 4"]
 284         initial_regs = [0] * 32
 285         initial_regs[4] = 0xffff6dc1
 286         initial_regs[22] = 0
 287         XER = 0xe00c0000
 288         CR = 0x50759999
 289
 290         self.add_case(Program(lst, bigendian), initial_regs,
 291                                 initial_sprs = {'XER': XER},
 292                                 initial_cr = CR)
 293
 294     def case_cmpli_microwatt(self):
 295         """microwatt 1.bin: cmpli
 296            123ac:   9c 79 8d 2a     cmpli   cr5,0,r13,31132
 297             gpr: 00000000301fc7a7 <- r13
 298             cr : 0000000090215393
 299             xer: so 1 ca 0 32 0 ov 0 32 0
 300
 301         """
 302
 303         lst = ["cmpli 5, 0, 13, 31132"]
 304         initial_regs = [0] * 32
 305         initial_regs[13] = 0x301fc7a7
 306         XER = 0xe00c0000
 307         CR = 0x90215393
 308
 309         self.add_case(Program(lst, bigendian), initial_regs,
 310                                 initial_sprs = {'XER': XER},
 311                                 initial_cr = CR)
 312
 313     def case_extsb(self):
 314         insns = ["extsb", "extsh", "extsw"]
 315         for i in range(10):
 316             choice = random.choice(insns)
 317             lst = [f"{choice} 3, 1"]
 318             print(lst)
 319             initial_regs = [0] * 32
 320             initial_regs[1] = random.randint(0, (1 << 64)-1)
 321             self.add_case(Program(lst, bigendian), initial_regs)
 322
 323     def case_cmpeqb(self):
 324         lst = ["cmpeqb cr1, 1, 2"]
 325         for i in range(20):
 326             initial_regs = [0] * 32
 327             initial_regs[1] = i
 328             initial_regs[2] = 0x0001030507090b0f
 329             self.add_case(Program(lst, bigendian), initial_regs, {})
 330