src/openpower/test/alu/alu_cases.py

   1 import random
   2 from openpower.test.common import TestAccumulatorBase
   3 from openpower.endian import bigendian
   4 from openpower.simulator.program import Program
   5 from openpower.decoder.selectable_int import SelectableInt
   6 from openpower.decoder.power_enums import XER_bits
   7 from openpower.decoder.isa.caller import special_sprs
   8 from openpower.test.state import ExpectedState
   9 import unittest
  10
  11
  12 class ALUTestCase(TestAccumulatorBase):
  13
  14     def case_1_regression(self):
  15         lst = [f"add. 3, 1, 2"]
  16         initial_regs = [0] * 32
  17         initial_regs[1] = 0xc523e996a8ff6215
  18         initial_regs[2] = 0xe1e5b9cc9864c4a8
  19         e = ExpectedState(pc=4)
  20         e.intregs[1] = 0xc523e996a8ff6215
  21         e.intregs[2] = 0xe1e5b9cc9864c4a8
  22         e.intregs[3] = 0xa709a363416426bd
  23         e.crregs[0] = 0x8
  24         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  25
  26     def case_2_regression(self):
  27         lst = [f"extsw 3, 1"]
  28         initial_regs = [0] * 32
  29         initial_regs[1] = 0xb6a1fc6c8576af91
  30         e = ExpectedState(pc=4)
  31         e.intregs[1] = 0xb6a1fc6c8576af91
  32         e.intregs[3] = 0xffffffff8576af91
  33         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  34
  35         lst = [f"subf 3, 1, 2"]
  36         initial_regs = [0] * 32
  37         initial_regs[1] = 0x3d7f3f7ca24bac7b
  38         initial_regs[2] = 0xf6b2ac5e13ee15c2
  39         e = ExpectedState(pc=4)
  40         e.intregs[1] = 0x3d7f3f7ca24bac7b
  41         e.intregs[2] = 0xf6b2ac5e13ee15c2
  42         e.intregs[3] = 0xb9336ce171a26947
  43         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  44
  45         lst = [f"subf 3, 1, 2"]
  46         initial_regs = [0] * 32
  47         initial_regs[1] = 0x833652d96c7c0058
  48         initial_regs[2] = 0x1c27ecff8a086c1a
  49         e = ExpectedState(pc=4)
  50         e.intregs[1] = 0x833652d96c7c0058
  51         e.intregs[2] = 0x1c27ecff8a086c1a
  52         e.intregs[3] = 0x98f19a261d8c6bc2
  53         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  54
  55         lst = [f"extsb 3, 1"]
  56         initial_regs = [0] * 32
  57         initial_regs[1] = 0x7f9497aaff900ea0
  58         e = ExpectedState(pc=4)
  59         e.intregs[1] = 0x7f9497aaff900ea0
  60         e.intregs[3] = 0xffffffffffffffa0
  61         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  62
  63         lst = [f"add 3, 1, 2"]
  64         initial_regs = [0] * 32
  65         initial_regs[1] = 0x2e08ae202742baf8
  66         initial_regs[2] = 0x86c43ece9efe5baa
  67         e = ExpectedState(pc=4)
  68         e.intregs[1] = 0x2e08ae202742baf8
  69         e.intregs[2] = 0x86c43ece9efe5baa
  70         e.intregs[3] = 0xb4cceceec64116a2
  71         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  72
  73     def case_rand(self):
  74         insns = ["add", "add.", "subf"]
  75         for i in range(40):
  76             choice = random.choice(insns)
  77             lst = [f"{choice} 3, 1, 2"]
  78             initial_regs = [0] * 32
  79             initial_regs[1] = random.randint(0, (1 << 64)-1)
  80             initial_regs[2] = random.randint(0, (1 << 64)-1)
  81
  82             e = ExpectedState(pc=4)
  83             e.intregs[1] = initial_regs[1]
  84             e.intregs[2] = initial_regs[2]
  85             if choice == "add":
  86                 result = initial_regs[1] + initial_regs[2]
  87                 if result < 0:
  88                     e.intregs[3] = (result + 2**64) & ((2**64)-1)
  89                 else:
  90                     e.intregs[3] = result & ((2**64)-1)
  91             elif choice == "add.":
  92                 result = initial_regs[1] + initial_regs[2]
  93                 if result < 0:
  94                     e.intregs[3] = (result + 2**64) & ((2**64)-1)
  95                 else:
  96                     e.intregs[3] = result & ((2**64)-1)
  97                 eq = 0
  98                 gt = 0
  99                 le = 0
 100                 if (e.intregs[3] & (1<<63)) != 0:
 101                     le = 1
 102                 elif e.intregs[3] == 0:
 103                     eq = 1
 104                 else:
 105                     gt = 1
 106                 e.crregs[0] = (eq<<1) | (gt<<2) | (le<<3)
 107             elif choice == "subf":
 108                 result = ~initial_regs[1] + initial_regs[2] + 1
 109                 if result < 0:
 110                     e.intregs[3] = (result + 2**64) & ((2**64)-1)
 111                 else:
 112                     e.intregs[3] = result & ((2**64)-1)
 113
 114             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 115
 116     def case_addme_ca_0(self):
 117         insns = ["addme", "addme.", "addmeo", "addmeo."]
 118         for choice in insns:
 119             lst = [f"{choice} 6, 16"]
 120             for value in [0x7ffffffff,
 121                           0xffff80000]:
 122                 initial_regs = [0] * 32
 123                 initial_regs[16] = value
 124                 initial_sprs = {}
 125                 xer = SelectableInt(0, 64)
 126                 xer[XER_bits['CA']] = 0  # input carry is 0 (see test below)
 127                 initial_sprs[special_sprs['XER']] = xer
 128
 129                 # create expected results.  pc should be 4 (one instruction)
 130                 e = ExpectedState(pc=4)
 131                 # input value should not be modified
 132                 e.intregs[16] = value
 133                 # carry-out should always occur
 134                 e.ca = 0x3
 135                 # create output value
 136                 if value == 0x7ffffffff:
 137                     e.intregs[6] = 0x7fffffffe
 138                 else:
 139                     e.intregs[6] = 0xffff7ffff
 140                 # CR version needs an expected CR
 141                 if '.' in choice:
 142                     e.crregs[0] = 0x4
 143                 self.add_case(Program(lst, bigendian),
 144                               initial_regs, initial_sprs,
 145                               expected=e)
 146
 147     def case_addme_ca_1(self):
 148         insns = ["addme", "addme.", "addmeo", "addmeo."]
 149         for choice in insns:
 150             lst = [f"{choice} 6, 16"]
 151             for value in [0x7ffffffff, # fails, bug #476
 152                           0xffff80000]:
 153                 initial_regs = [0] * 32
 154                 initial_regs[16] = value
 155                 initial_sprs = {}
 156                 xer = SelectableInt(0, 64)
 157                 xer[XER_bits['CA']] = 1 # input carry is 1 (differs from above)
 158                 initial_sprs[special_sprs['XER']] = xer
 159                 e = ExpectedState(pc=4)
 160                 e.intregs[16] = value
 161                 e.ca = 0x3
 162                 if value == 0x7ffffffff:
 163                     e.intregs[6] = 0x7ffffffff
 164                 else:
 165                     e.intregs[6] = 0xffff80000
 166                 if '.' in choice:
 167                     e.crregs[0] = 0x4
 168                 self.add_case(Program(lst, bigendian),
 169                               initial_regs, initial_sprs, expected=e)
 170
 171     def case_addme_ca_so_4(self):
 172         """test of SO being set
 173         """
 174         lst = ["addmeo. 6, 16"]
 175         initial_regs = [0] * 32
 176         initial_regs[16] = 0x7fffffffffffffff
 177         initial_sprs = {}
 178         xer = SelectableInt(0, 64)
 179         xer[XER_bits['CA']] = 1
 180         initial_sprs[special_sprs['XER']] = xer
 181         e = ExpectedState(pc=4)
 182         e.intregs[16] = 0x7fffffffffffffff
 183         e.intregs[6] = 0x7fffffffffffffff
 184         e.ca = 0x3
 185         e.crregs[0] = 0x4
 186         self.add_case(Program(lst, bigendian),
 187                       initial_regs, initial_sprs, expected=e)
 188
 189     def case_addme_ca_so_3(self):
 190         """bug where SO does not get passed through to CR0
 191         """
 192         lst = ["addme. 6, 16"]
 193         initial_regs = [0] * 32
 194         initial_regs[16] = 0x7ffffffff
 195         initial_sprs = {}
 196         xer = SelectableInt(0, 64)
 197         xer[XER_bits['CA']] = 1
 198         xer[XER_bits['SO']] = 1
 199         initial_sprs[special_sprs['XER']] = xer
 200         e = ExpectedState(pc=4)
 201         e.intregs[16] = 0x7ffffffff
 202         e.intregs[6] = 0x7ffffffff
 203         e.crregs[0] = 0x5
 204         e.so = 0x1
 205         e.ca = 0x3
 206         self.add_case(Program(lst, bigendian),
 207                       initial_regs, initial_sprs, expected=e)
 208
 209     def case_addze(self):
 210         insns = ["addze", "addze.", "addzeo", "addzeo."]
 211         for choice in insns:
 212             lst = [f"{choice} 6, 16"]
 213             initial_regs = [0] * 32
 214             initial_regs[16] = 0x00ff00ff00ff0080
 215             e = ExpectedState(pc=4)
 216             e.intregs[16] = 0xff00ff00ff0080
 217             e.intregs[6] = 0xff00ff00ff0080
 218             if '.' in choice:
 219                 e.crregs[0] = 0x4
 220             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 221
 222     def case_addis_nonzero_r0_regression(self):
 223         lst = [f"addis 3, 0, 1"]
 224         print(lst)
 225         initial_regs = [0] * 32
 226         initial_regs[0] = 5
 227         e = ExpectedState(initial_regs, pc=4)
 228         e.intregs[3] = 0x10000
 229         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 230
 231     def case_addis_nonzero_r0(self):
 232         for i in range(10):
 233             imm = random.randint(-(1 << 15), (1 << 15)-1)
 234             lst = [f"addis 3, 0, {imm}"]
 235             print(lst)
 236             initial_regs = [0] * 32
 237             initial_regs[0] = random.randint(0, (1 << 64)-1)
 238             e = ExpectedState(pc=4)
 239             e.intregs[0] = initial_regs[0]
 240             e.intregs[3] = (imm << 16) & ((1<<64)-1)
 241             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 242
 243     def case_rand_imm(self):
 244         insns = ["addi", "addis", "subfic"]
 245         for i in range(10):
 246             choice = random.choice(insns)
 247             imm = random.randint(-(1 << 15), (1 << 15)-1)
 248             lst = [f"{choice} 3, 1, {imm}"]
 249             print(lst)
 250             initial_regs = [0] * 32
 251             initial_regs[1] = random.randint(0, (1 << 64)-1)
 252
 253             e = ExpectedState(pc=4)
 254             e.intregs[1] = initial_regs[1]
 255             if choice == "addi":
 256                 result = initial_regs[1] + imm
 257                 e.intregs[3] = result & ((2**64)-1)
 258             elif choice == "addis":
 259                 result = initial_regs[1] + (imm<<16)
 260                 e.intregs[3] = result & ((2**64)-1)
 261             elif choice == "subfic":
 262                 result = ~initial_regs[1] + imm + 1
 263                 value = (~initial_regs[1]+2**64) + (imm) + 1
 264                 if imm < 0:
 265                     value += 2**64
 266                 carry_out = value & (1<<64) != 0
 267                 value = (~initial_regs[1]+2**64 & 0xffff_ffff) + imm + 1
 268                 if imm < 0:
 269                     value += 2**32
 270                 carry_out32 = value & (1<<32) != 0
 271                 e.intregs[3] = result & ((2**64)-1)
 272                 e.ca = carry_out | (carry_out32<<1)
 273
 274             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 275
 276     def case_0_adde(self):
 277         lst = ["adde. 5, 6, 7"]
 278         for i in range(10):
 279             initial_regs = [0] * 32
 280             initial_regs[6] = random.randint(0, (1 << 64)-1)
 281             initial_regs[7] = random.randint(0, (1 << 64)-1)
 282             initial_sprs = {}
 283             xer = SelectableInt(0, 64)
 284             xer[XER_bits['CA']] = 1
 285             initial_sprs[special_sprs['XER']] = xer
 286             # calculate result *including carry* and mask it to 64-bit
 287             # (if it overflows, we don't care, because this is not addeo)
 288             result = 1 + initial_regs[6] + initial_regs[7]
 289             carry_out = result & (1<<64) != 0 # detect 65th bit as carry-out?
 290             carry_out32 = (initial_regs[6] & 0xffff_ffff) + \
 291                     (initial_regs[7] & 0xffff_ffff) & (1<<32) != 0
 292             result = result & ((1<<64)-1) # round
 293             eq = 0
 294             gt = 0
 295             le = 0
 296             if (result & (1<<63)) != 0:
 297                 le = 1
 298             elif result == 0:
 299                 eq = 1
 300             else:
 301                 gt = 1
 302             # now construct the state
 303             e = ExpectedState(pc=4)
 304             e.intregs[6] = initial_regs[6] # should be same as initial
 305             e.intregs[7] = initial_regs[7] # should be same as initial
 306             e.intregs[5] = result
 307             # carry_out goes into bit 0 of ca, carry_out32 into bit 1
 308             e.ca = carry_out | (carry_out32<<1)
 309             # eq goes into bit 1 of CR0, gt into bit 2, le into bit 3.
 310             # SO goes into bit 0 but overflow doesn't occur here [we hope]
 311             e.crregs[0] = (eq<<1) | (gt<<2) | (le<<3)
 312
 313             self.add_case(Program(lst, bigendian),
 314                           initial_regs, initial_sprs, expected=e)
 315
 316     def case_cmp(self):
 317         lst = ["subf. 1, 6, 7",
 318                "cmp cr2, 1, 6, 7"]
 319         initial_regs = [0] * 32
 320         initial_regs[6] = 0x10
 321         initial_regs[7] = 0x05
 322         e = ExpectedState(pc=8)
 323         e.intregs[6] = 0x10
 324         e.intregs[7] = 0x5
 325         e.intregs[1] = 0xfffffffffffffff5
 326         e.crregs[0] = 0x8
 327         e.crregs[2] = 0x4
 328         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 329
 330     def case_cmp2(self):
 331         lst = ["cmp cr2, 0, 2, 3"]
 332         initial_regs = [0] * 32
 333         initial_regs[2] = 0xffffffffaaaaaaaa
 334         initial_regs[3] = 0x00000000aaaaaaaa
 335         e = ExpectedState(pc=4)
 336         e.intregs[2] = 0xffffffffaaaaaaaa
 337         e.intregs[3] = 0xaaaaaaaa
 338         e.crregs[2] = 0x2
 339         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 340
 341         lst = ["cmp cr2, 0, 4, 5"]
 342         initial_regs = [0] * 32
 343         initial_regs[4] = 0x00000000aaaaaaaa
 344         initial_regs[5] = 0xffffffffaaaaaaaa
 345         e = ExpectedState(pc=4)
 346         e.intregs[4] = 0xaaaaaaaa
 347         e.intregs[5] = 0xffffffffaaaaaaaa
 348         e.crregs[2] = 0x2
 349         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 350
 351     def case_cmp3(self):
 352         lst = ["cmp cr2, 1, 2, 3"]
 353         initial_regs = [0] * 32
 354         initial_regs[2] = 0xffffffffaaaaaaaa
 355         initial_regs[3] = 0x00000000aaaaaaaa
 356         e = ExpectedState(pc=4)
 357         e.intregs[2] = 0xffffffffaaaaaaaa
 358         e.intregs[3] = 0xaaaaaaaa
 359         e.crregs[2] = 0x8
 360         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 361
 362         lst = ["cmp cr2, 1, 4, 5"]
 363         initial_regs = [0] * 32
 364         initial_regs[4] = 0x00000000aaaaaaaa
 365         initial_regs[5] = 0xffffffffaaaaaaaa
 366         e = ExpectedState(pc=4)
 367         e.intregs[4] = 0xaaaaaaaa
 368         e.intregs[5] = 0xffffffffaaaaaaaa
 369         e.crregs[2] = 0x4
 370         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 371
 372     def case_cmpl_microwatt_0(self):
 373         """microwatt 1.bin:
 374            115b8:   40 50 d1 7c     .long 0x7cd15040 # cmpl 6, 0, 17, 10
 375             register_file.vhdl: Reading GPR 11 000000000001C026
 376             register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
 377             cr_file.vhdl: Reading CR 35055050
 378             cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
 379         """
 380
 381         lst = ["cmpl 6, 0, 17, 10"]
 382         initial_regs = [0] * 32
 383         initial_regs[0x11] = 0x1c026
 384         initial_regs[0xa] =  0xFEDF3FFF0001C025
 385         XER = 0xe00c0000
 386         CR = 0x35055050
 387
 388         e = ExpectedState(pc=4)
 389         e.intregs[10] = 0xfedf3fff0001c025
 390         e.intregs[17] = 0x1c026
 391         e.crregs[0] = 0x3
 392         e.crregs[1] = 0x5
 393         e.crregs[3] = 0x5
 394         e.crregs[4] = 0x5
 395         e.crregs[6] = 0x5
 396         e.so = 0x1
 397         e.ov = 0x3
 398         e.ca = 0x3
 399
 400         self.add_case(Program(lst, bigendian), initial_regs,
 401                                 initial_sprs = {'XER': XER},
 402                                 initial_cr = CR, expected=e)
 403
 404     def case_cmpl_microwatt_0_disasm(self):
 405         """microwatt 1.bin: disassembled version
 406            115b8:   40 50 d1 7c     .long 0x7cd15040 # cmpl 6, 0, 17, 10
 407             register_file.vhdl: Reading GPR 11 000000000001C026
 408             register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
 409             cr_file.vhdl: Reading CR 35055050
 410             cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
 411         """
 412
 413         dis = ["cmpl 6, 0, 17, 10"]
 414         lst = bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
 415         initial_regs = [0] * 32
 416         initial_regs[0x11] = 0x1c026
 417         initial_regs[0xa] =  0xFEDF3FFF0001C025
 418         XER = 0xe00c0000
 419         CR = 0x35055050
 420
 421         e = ExpectedState(pc=4)
 422         e.intregs[10] = 0xfedf3fff0001c025
 423         e.intregs[17] = 0x1c026
 424         e.crregs[0] = 0x3
 425         e.crregs[1] = 0x5
 426         e.crregs[3] = 0x5
 427         e.crregs[4] = 0x5
 428         e.crregs[6] = 0x5
 429         e.so = 0x1
 430         e.ov = 0x3
 431         e.ca = 0x3
 432
 433         p = Program(lst, bigendian)
 434         p.assembly = '\n'.join(dis)+'\n'
 435         self.add_case(p, initial_regs,
 436                                 initial_sprs = {'XER': XER},
 437                                 initial_cr = CR, expected=e)
 438
 439     def case_cmplw_microwatt_1(self):
 440         """microwatt 1.bin:
 441            10d94:   40 20 96 7c     cmplw   cr1,r22,r4
 442             gpr: 00000000ffff6dc1 <- r4
 443             gpr: 0000000000000000 <- r22
 444         """
 445
 446         lst = ["cmpl 1, 0, 22, 4"]
 447         initial_regs = [0] * 32
 448         initial_regs[4] = 0xffff6dc1
 449         initial_regs[22] = 0
 450         XER = 0xe00c0000
 451         CR = 0x50759999
 452
 453         e = ExpectedState(pc=4)
 454         e.intregs[4] = 0xffff6dc1
 455         e.crregs[0] = 0x5
 456         e.crregs[1] = 0x9
 457         e.crregs[2] = 0x7
 458         e.crregs[3] = 0x5
 459         e.crregs[4] = 0x9
 460         e.crregs[5] = 0x9
 461         e.crregs[6] = 0x9
 462         e.crregs[7] = 0x9
 463         e.so = 0x1
 464         e.ov = 0x3
 465         e.ca = 0x3
 466
 467         self.add_case(Program(lst, bigendian), initial_regs,
 468                                 initial_sprs = {'XER': XER},
 469                                 initial_cr = CR, expected=e)
 470
 471     def case_cmpli_microwatt(self):
 472         """microwatt 1.bin: cmpli
 473            123ac:   9c 79 8d 2a     cmpli   cr5,0,r13,31132
 474             gpr: 00000000301fc7a7 <- r13
 475             cr : 0000000090215393
 476             xer: so 1 ca 0 32 0 ov 0 32 0
 477
 478         """
 479
 480         lst = ["cmpli 5, 0, 13, 31132"]
 481         initial_regs = [0] * 32
 482         initial_regs[13] = 0x301fc7a7
 483         XER = 0xe00c0000
 484         CR = 0x90215393
 485
 486         e = ExpectedState(pc=4)
 487         e.intregs[13] = 0x301fc7a7
 488         e.crregs[0] = 0x9
 489         e.crregs[2] = 0x2
 490         e.crregs[3] = 0x1
 491         e.crregs[4] = 0x5
 492         e.crregs[5] = 0x5
 493         e.crregs[6] = 0x9
 494         e.crregs[7] = 0x3
 495         e.so = 0x1
 496         e.ov = 0x3
 497         e.ca = 0x3
 498
 499         self.add_case(Program(lst, bigendian), initial_regs,
 500                                 initial_sprs = {'XER': XER},
 501                                 initial_cr = CR, expected=e)
 502
 503     def case_extsb(self):
 504         insns = ["extsb", "extsh", "extsw"]
 505         for i in range(10):
 506             choice = random.choice(insns)
 507             lst = [f"{choice} 3, 1"]
 508             print(lst)
 509             initial_regs = [0] * 32
 510             initial_regs[1] = random.randint(0, (1 << 64)-1)
 511
 512             e = ExpectedState(pc=4)
 513             e.intregs[1] = initial_regs[1]
 514             if choice == "extsb":
 515                 s = ((initial_regs[1] & 0x1000_0000_0000_0080)>>7)&0x1
 516                 if s == 1:
 517                     value = 0xffff_ffff_ffff_ff<<8
 518                 else:
 519                     value = 0x0
 520                 e.intregs[3] = value | (initial_regs[1] & 0xff)
 521             elif choice == "extsh":
 522                 s = ((initial_regs[1] & 0x1000_0000_0000_8000)>>15)&0x1
 523                 if s == 1:
 524                     value = 0xffff_ffff_ffff<<16
 525                 else:
 526                     value = 0x0
 527                 e.intregs[3] = value | (initial_regs[1] & 0xffff)
 528             else:
 529                 s = ((initial_regs[1] & 0x1000_0000_8000_0000)>>31)&0x1
 530                 if s == 1:
 531                     value = 0xffff_ffff<<32
 532                 else:
 533                     value = 0x0
 534                 e.intregs[3] = value | (initial_regs[1] & 0xffff_ffff)
 535
 536             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 537
 538     def case_cmpeqb(self):
 539         lst = ["cmpeqb cr1, 1, 2"]
 540         for i in range(20):
 541             initial_regs = [0] * 32
 542             initial_regs[1] = i
 543             initial_regs[2] = 0x0001030507090b0f
 544
 545             e = ExpectedState(pc=4)
 546             e.intregs[1] = i
 547             e.intregs[2] = 0x1030507090b0f
 548             matlst = [ 0x00, 0x01, 0x03, 0x05, 0x07, 0x09, 0x0b, 0x0f ]
 549             for j in matlst:
 550                 if j == i:
 551                     e.crregs[1] = 0x4
 552
 553             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 554