src/openpower/test/alu/alu_cases.py

   1 import random
   2 from openpower.test.common import TestAccumulatorBase
   3 from openpower.endian import bigendian
   4 from openpower.simulator.program import Program
   5 from openpower.decoder.selectable_int import SelectableInt
   6 from openpower.decoder.power_enums import XER_bits
   7 from openpower.decoder.isa.caller import special_sprs
   8 from openpower.test.state import ExpectedState
   9 import unittest
  10
  11
  12 class ALUTestCase(TestAccumulatorBase):
  13
  14     def case_1_regression(self):
  15         lst = [f"add. 3, 1, 2"]
  16         initial_regs = [0] * 32
  17         initial_regs[1] = 0xc523e996a8ff6215
  18         initial_regs[2] = 0xe1e5b9cc9864c4a8
  19         e = ExpectedState(pc=4)
  20         e.intregs[1] = 0xc523e996a8ff6215
  21         e.intregs[2] = 0xe1e5b9cc9864c4a8
  22         e.intregs[3] = 0xa709a363416426bd
  23         e.crregs[0] = 0x8
  24         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  25
  26     def case_2_regression(self):
  27         lst = [f"extsw 3, 1"]
  28         initial_regs = [0] * 32
  29         initial_regs[1] = 0xb6a1fc6c8576af91
  30         e = ExpectedState(pc=4)
  31         e.intregs[1] = 0xb6a1fc6c8576af91
  32         e.intregs[3] = 0xffffffff8576af91
  33         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  34
  35         lst = [f"subf 3, 1, 2"]
  36         initial_regs = [0] * 32
  37         initial_regs[1] = 0x3d7f3f7ca24bac7b
  38         initial_regs[2] = 0xf6b2ac5e13ee15c2
  39         e = ExpectedState(pc=4)
  40         e.intregs[1] = 0x3d7f3f7ca24bac7b
  41         e.intregs[2] = 0xf6b2ac5e13ee15c2
  42         e.intregs[3] = 0xb9336ce171a26947
  43         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  44
  45         lst = [f"subf 3, 1, 2"]
  46         initial_regs = [0] * 32
  47         initial_regs[1] = 0x833652d96c7c0058
  48         initial_regs[2] = 0x1c27ecff8a086c1a
  49         e = ExpectedState(pc=4)
  50         e.intregs[1] = 0x833652d96c7c0058
  51         e.intregs[2] = 0x1c27ecff8a086c1a
  52         e.intregs[3] = 0x98f19a261d8c6bc2
  53         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  54
  55         lst = [f"extsb 3, 1"]
  56         initial_regs = [0] * 32
  57         initial_regs[1] = 0x7f9497aaff900ea0
  58         e = ExpectedState(pc=4)
  59         e.intregs[1] = 0x7f9497aaff900ea0
  60         e.intregs[3] = 0xffffffffffffffa0
  61         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  62
  63         lst = [f"add 3, 1, 2"]
  64         initial_regs = [0] * 32
  65         initial_regs[1] = 0x2e08ae202742baf8
  66         initial_regs[2] = 0x86c43ece9efe5baa
  67         e = ExpectedState(pc=4)
  68         e.intregs[1] = 0x2e08ae202742baf8
  69         e.intregs[2] = 0x86c43ece9efe5baa
  70         e.intregs[3] = 0xb4cceceec64116a2
  71         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  72
  73     def case_rand(self):
  74         insns = ["add", "add.", "subf"]
  75         for i in range(40):
  76             choice = random.choice(insns)
  77             lst = [f"{choice} 3, 1, 2"]
  78             initial_regs = [0] * 32
  79             initial_regs[1] = random.randint(0, (1 << 64)-1)
  80             initial_regs[2] = random.randint(0, (1 << 64)-1)
  81
  82             e = ExpectedState(pc=4)
  83             e.intregs[1] = initial_regs[1]
  84             e.intregs[2] = initial_regs[2]
  85             if choice == "add":
  86                 result = initial_regs[1] + initial_regs[2]
  87                 if result < 0:
  88                     e.intregs[3] = (result + 2**64) & ((2**64)-1)
  89                 else:
  90                     e.intregs[3] = result & ((2**64)-1)
  91             elif choice == "add.":
  92                 result = initial_regs[1] + initial_regs[2]
  93                 if result < 0:
  94                     e.intregs[3] = (result + 2**64) & ((2**64)-1)
  95                 else:
  96                     e.intregs[3] = result & ((2**64)-1)
  97                 eq = 0
  98                 gt = 0
  99                 le = 0
 100                 if (e.intregs[3] & (1<<63)) != 0:
 101                     le = 1
 102                 elif e.intregs[3] == 0:
 103                     eq = 1
 104                 else:
 105                     gt = 1
 106                 e.crregs[0] = (eq<<1) | (gt<<2) | (le<<3)
 107             elif choice == "subf":
 108                 result = ~initial_regs[1] + initial_regs[2] + 1
 109                 if result < 0:
 110                     e.intregs[3] = (result + 2**64) & ((2**64)-1)
 111                 else:
 112                     e.intregs[3] = result & ((2**64)-1)
 113
 114             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 115
 116     def case_addme_ca_0(self):
 117         insns = ["addme", "addme.", "addmeo", "addmeo."]
 118         for choice in insns:
 119             lst = [f"{choice} 6, 16"]
 120             for value in [0x7ffffffff,
 121                           0xffff80000]:
 122                 initial_regs = [0] * 32
 123                 initial_regs[16] = value
 124                 initial_sprs = {}
 125                 xer = SelectableInt(0, 64)
 126                 xer[XER_bits['CA']] = 0  # input carry is 0 (see test below)
 127                 initial_sprs[special_sprs['XER']] = xer
 128
 129                 # create expected results.  pc should be 4 (one instruction)
 130                 e = ExpectedState(pc=4)
 131                 # input value should not be modified
 132                 e.intregs[16] = value
 133                 # carry-out should always occur
 134                 e.ca = 0x3
 135                 # create output value
 136                 if value == 0x7ffffffff:
 137                     e.intregs[6] = 0x7fffffffe
 138                 else:
 139                     e.intregs[6] = 0xffff7ffff
 140                 # CR version needs an expected CR
 141                 if '.' in choice:
 142                     e.crregs[0] = 0x4
 143                 self.add_case(Program(lst, bigendian),
 144                               initial_regs, initial_sprs,
 145                               expected=e)
 146
 147     def case_addme_ca_1(self):
 148         insns = ["addme", "addme.", "addmeo", "addmeo."]
 149         for choice in insns:
 150             lst = [f"{choice} 6, 16"]
 151             for value in [0x7ffffffff, # fails, bug #476
 152                           0xffff80000]:
 153                 initial_regs = [0] * 32
 154                 initial_regs[16] = value
 155                 initial_sprs = {}
 156                 xer = SelectableInt(0, 64)
 157                 xer[XER_bits['CA']] = 1 # input carry is 1 (differs from above)
 158                 initial_sprs[special_sprs['XER']] = xer
 159                 e = ExpectedState(pc=4)
 160                 e.intregs[16] = value
 161                 e.ca = 0x3
 162                 if value == 0x7ffffffff:
 163                     e.intregs[6] = 0x7ffffffff
 164                 else:
 165                     e.intregs[6] = 0xffff80000
 166                 if '.' in choice:
 167                     e.crregs[0] = 0x4
 168                 self.add_case(Program(lst, bigendian),
 169                               initial_regs, initial_sprs, expected=e)
 170
 171     def case_addme_ca_so_4(self):
 172         """test of SO being set
 173         """
 174         lst = ["addmeo. 6, 16"]
 175         initial_regs = [0] * 32
 176         initial_regs[16] = 0x7fffffffffffffff
 177         initial_sprs = {}
 178         xer = SelectableInt(0, 64)
 179         xer[XER_bits['CA']] = 1
 180         initial_sprs[special_sprs['XER']] = xer
 181         e = ExpectedState(pc=4)
 182         e.intregs[16] = 0x7fffffffffffffff
 183         e.intregs[6] = 0x7fffffffffffffff
 184         e.ca = 0x3
 185         e.crregs[0] = 0x4
 186         self.add_case(Program(lst, bigendian),
 187                       initial_regs, initial_sprs, expected=e)
 188
 189     def case_addme_ca_so_3(self):
 190         """bug where SO does not get passed through to CR0
 191         """
 192         lst = ["addme. 6, 16"]
 193         initial_regs = [0] * 32
 194         initial_regs[16] = 0x7ffffffff
 195         initial_sprs = {}
 196         xer = SelectableInt(0, 64)
 197         xer[XER_bits['CA']] = 1
 198         xer[XER_bits['SO']] = 1
 199         initial_sprs[special_sprs['XER']] = xer
 200         e = ExpectedState(pc=4)
 201         e.intregs[16] = 0x7ffffffff
 202         e.intregs[6] = 0x7ffffffff
 203         e.crregs[0] = 0x5
 204         e.so = 0x1
 205         e.ca = 0x3
 206         self.add_case(Program(lst, bigendian),
 207                       initial_regs, initial_sprs, expected=e)
 208
 209     def case_addze(self):
 210         insns = ["addze", "addze.", "addzeo", "addzeo."]
 211         for choice in insns:
 212             lst = [f"{choice} 6, 16"]
 213             initial_regs = [0] * 32
 214             initial_regs[16] = 0x00ff00ff00ff0080
 215             e = ExpectedState(pc=4)
 216             e.intregs[16] = 0xff00ff00ff0080
 217             e.intregs[6] = 0xff00ff00ff0080
 218             if '.' in choice:
 219                 e.crregs[0] = 0x4
 220             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 221
 222     def case_addis_nonzero_r0_regression(self):
 223         lst = [f"addis 3, 0, 1"]
 224         print(lst)
 225         initial_regs = [0] * 32
 226         initial_regs[0] = 5
 227         e = ExpectedState(initial_regs, pc=4)
 228         e.intregs[3] = 0x10000
 229         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 230
 231     def case_addis_nonzero_r0(self):
 232         for i in range(10):
 233             imm = random.randint(-(1 << 15), (1 << 15)-1)
 234             lst = [f"addis 3, 0, {imm}"]
 235             print(lst)
 236             initial_regs = [0] * 32
 237             initial_regs[0] = random.randint(0, (1 << 64)-1)
 238             e = ExpectedState(pc=4)
 239             e.intregs[0] = initial_regs[0]
 240             if imm < 0:
 241                 e.intregs[3] = (imm + 2**48)<<16
 242             else:
 243                 e.intregs[3] = imm << 16
 244             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 245
 246     def case_rand_imm(self):
 247         insns = ["addi", "addis", "subfic"]
 248         for i in range(10):
 249             choice = random.choice(insns)
 250             imm = random.randint(-(1 << 15), (1 << 15)-1)
 251             lst = [f"{choice} 3, 1, {imm}"]
 252             print(lst)
 253             initial_regs = [0] * 32
 254             initial_regs[1] = random.randint(0, (1 << 64)-1)
 255
 256             e = ExpectedState(pc=4)
 257             e.intregs[1] = initial_regs[1]
 258             if choice == "addi":
 259                 result = initial_regs[1] + imm
 260                 if result < 0:
 261                     e.intregs[3] = (result + 2**64) & ((2**64)-1)
 262                 else:
 263                     e.intregs[3] = result & ((2**64)-1)
 264             elif choice == "addis":
 265                 result = initial_regs[1] + (imm<<16)
 266                 if result < 0:
 267                     e.intregs[3] = (result + 2**64) & ((2**64)-1)
 268                 else:
 269                     e.intregs[3] = result & ((2**64)-1)
 270             elif choice == "subfic":
 271                 result = ~initial_regs[1] + imm + 1
 272                 if imm >= 0:
 273                     value = (~initial_regs[1]+2**64) + (imm) + 1
 274                 else:
 275                     value = (~initial_regs[1]+2**64) + (imm+2**64) + 1
 276                 carry_out = value & (1<<64) != 0
 277                 if imm >= 0:
 278                     carry_out32 = (((~initial_regs[1]+2**64) & 0xffff_ffff) + \
 279                             (imm) + 1) & (1<<32)
 280                 else:
 281                     carry_out32 = (((~initial_regs[1]+2**64) & 0xffff_ffff) + \
 282                             (imm+2**32) + 1) & (1<<32)
 283                 if result < 0:
 284                     e.intregs[3] = (result + 2**64) & ((2**64)-1)
 285                 else:
 286                     e.intregs[3] = result & ((2**64)-1)
 287                 e.ca = carry_out | (carry_out32>>31)
 288
 289             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 290
 291     def case_0_adde(self):
 292         lst = ["adde. 5, 6, 7"]
 293         for i in range(10):
 294             initial_regs = [0] * 32
 295             initial_regs[6] = random.randint(0, (1 << 64)-1)
 296             initial_regs[7] = random.randint(0, (1 << 64)-1)
 297             initial_sprs = {}
 298             xer = SelectableInt(0, 64)
 299             xer[XER_bits['CA']] = 1
 300             initial_sprs[special_sprs['XER']] = xer
 301             # calculate result *including carry* and mask it to 64-bit
 302             # (if it overflows, we don't care, because this is not addeo)
 303             result = 1 + initial_regs[6] + initial_regs[7]
 304             carry_out = result & (1<<64) != 0 # detect 65th bit as carry-out?
 305             carry_out32 = ((initial_regs[6] & 0xffff_ffff) + \
 306                     (initial_regs[7] & 0xffff_ffff)) & (1<<32)
 307             result = result & ((1<<64)-1) # round
 308             eq = 0
 309             gt = 0
 310             le = 0
 311             if (result & (1<<63)) != 0:
 312                 le = 1
 313             elif result == 0:
 314                 eq = 1
 315             else:
 316                 gt = 1
 317             # now construct the state
 318             e = ExpectedState(pc=4)
 319             e.intregs[6] = initial_regs[6] # should be same as initial
 320             e.intregs[7] = initial_regs[7] # should be same as initial
 321             e.intregs[5] = result
 322             # carry_out goes into bit 0 of ca, carry_out32 into bit 1
 323             e.ca = carry_out | (carry_out32>>31)
 324             # eq goes into bit 1 of CR0, gt into bit 2, le into bit 3.
 325             # SO goes into bit 0 but overflow doesn't occur here [we hope]
 326             e.crregs[0] = (eq<<1) | (gt<<2) | (le<<3)
 327
 328             self.add_case(Program(lst, bigendian),
 329                           initial_regs, initial_sprs, expected=e)
 330
 331     def case_cmp(self):
 332         lst = ["subf. 1, 6, 7",
 333                "cmp cr2, 1, 6, 7"]
 334         initial_regs = [0] * 32
 335         initial_regs[6] = 0x10
 336         initial_regs[7] = 0x05
 337         e = ExpectedState(pc=8)
 338         e.intregs[6] = 0x10
 339         e.intregs[7] = 0x5
 340         e.intregs[1] = 0xfffffffffffffff5
 341         e.crregs[0] = 0x8
 342         e.crregs[2] = 0x4
 343         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 344
 345     def case_cmp2(self):
 346         lst = ["cmp cr2, 0, 2, 3"]
 347         initial_regs = [0] * 32
 348         initial_regs[2] = 0xffffffffaaaaaaaa
 349         initial_regs[3] = 0x00000000aaaaaaaa
 350         e = ExpectedState(pc=4)
 351         e.intregs[2] = 0xffffffffaaaaaaaa
 352         e.intregs[3] = 0xaaaaaaaa
 353         e.crregs[2] = 0x2
 354         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 355
 356         lst = ["cmp cr2, 0, 4, 5"]
 357         initial_regs = [0] * 32
 358         initial_regs[4] = 0x00000000aaaaaaaa
 359         initial_regs[5] = 0xffffffffaaaaaaaa
 360         e = ExpectedState(pc=4)
 361         e.intregs[4] = 0xaaaaaaaa
 362         e.intregs[5] = 0xffffffffaaaaaaaa
 363         e.crregs[2] = 0x2
 364         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 365
 366     def case_cmp3(self):
 367         lst = ["cmp cr2, 1, 2, 3"]
 368         initial_regs = [0] * 32
 369         initial_regs[2] = 0xffffffffaaaaaaaa
 370         initial_regs[3] = 0x00000000aaaaaaaa
 371         e = ExpectedState(pc=4)
 372         e.intregs[2] = 0xffffffffaaaaaaaa
 373         e.intregs[3] = 0xaaaaaaaa
 374         e.crregs[2] = 0x8
 375         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 376
 377         lst = ["cmp cr2, 1, 4, 5"]
 378         initial_regs = [0] * 32
 379         initial_regs[4] = 0x00000000aaaaaaaa
 380         initial_regs[5] = 0xffffffffaaaaaaaa
 381         e = ExpectedState(pc=4)
 382         e.intregs[4] = 0xaaaaaaaa
 383         e.intregs[5] = 0xffffffffaaaaaaaa
 384         e.crregs[2] = 0x4
 385         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 386
 387     def case_cmpl_microwatt_0(self):
 388         """microwatt 1.bin:
 389            115b8:   40 50 d1 7c     .long 0x7cd15040 # cmpl 6, 0, 17, 10
 390             register_file.vhdl: Reading GPR 11 000000000001C026
 391             register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
 392             cr_file.vhdl: Reading CR 35055050
 393             cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
 394         """
 395
 396         lst = ["cmpl 6, 0, 17, 10"]
 397         initial_regs = [0] * 32
 398         initial_regs[0x11] = 0x1c026
 399         initial_regs[0xa] =  0xFEDF3FFF0001C025
 400         XER = 0xe00c0000
 401         CR = 0x35055050
 402
 403         e = ExpectedState(pc=4)
 404         e.intregs[10] = 0xfedf3fff0001c025
 405         e.intregs[17] = 0x1c026
 406         e.crregs[0] = 0x3
 407         e.crregs[1] = 0x5
 408         e.crregs[3] = 0x5
 409         e.crregs[4] = 0x5
 410         e.crregs[6] = 0x5
 411         e.so = 0x1
 412         e.ov = 0x3
 413         e.ca = 0x3
 414
 415         self.add_case(Program(lst, bigendian), initial_regs,
 416                                 initial_sprs = {'XER': XER},
 417                                 initial_cr = CR, expected=e)
 418
 419     def case_cmpl_microwatt_0_disasm(self):
 420         """microwatt 1.bin: disassembled version
 421            115b8:   40 50 d1 7c     .long 0x7cd15040 # cmpl 6, 0, 17, 10
 422             register_file.vhdl: Reading GPR 11 000000000001C026
 423             register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
 424             cr_file.vhdl: Reading CR 35055050
 425             cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
 426         """
 427
 428         dis = ["cmpl 6, 0, 17, 10"]
 429         lst = bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
 430         initial_regs = [0] * 32
 431         initial_regs[0x11] = 0x1c026
 432         initial_regs[0xa] =  0xFEDF3FFF0001C025
 433         XER = 0xe00c0000
 434         CR = 0x35055050
 435
 436         e = ExpectedState(pc=4)
 437         e.intregs[10] = 0xfedf3fff0001c025
 438         e.intregs[17] = 0x1c026
 439         e.crregs[0] = 0x3
 440         e.crregs[1] = 0x5
 441         e.crregs[3] = 0x5
 442         e.crregs[4] = 0x5
 443         e.crregs[6] = 0x5
 444         e.so = 0x1
 445         e.ov = 0x3
 446         e.ca = 0x3
 447
 448         p = Program(lst, bigendian)
 449         p.assembly = '\n'.join(dis)+'\n'
 450         self.add_case(p, initial_regs,
 451                                 initial_sprs = {'XER': XER},
 452                                 initial_cr = CR, expected=e)
 453
 454     def case_cmplw_microwatt_1(self):
 455         """microwatt 1.bin:
 456            10d94:   40 20 96 7c     cmplw   cr1,r22,r4
 457             gpr: 00000000ffff6dc1 <- r4
 458             gpr: 0000000000000000 <- r22
 459         """
 460
 461         lst = ["cmpl 1, 0, 22, 4"]
 462         initial_regs = [0] * 32
 463         initial_regs[4] = 0xffff6dc1
 464         initial_regs[22] = 0
 465         XER = 0xe00c0000
 466         CR = 0x50759999
 467
 468         e = ExpectedState(pc=4)
 469         e.intregs[4] = 0xffff6dc1
 470         e.crregs[0] = 0x5
 471         e.crregs[1] = 0x9
 472         e.crregs[2] = 0x7
 473         e.crregs[3] = 0x5
 474         e.crregs[4] = 0x9
 475         e.crregs[5] = 0x9
 476         e.crregs[6] = 0x9
 477         e.crregs[7] = 0x9
 478         e.so = 0x1
 479         e.ov = 0x3
 480         e.ca = 0x3
 481
 482         self.add_case(Program(lst, bigendian), initial_regs,
 483                                 initial_sprs = {'XER': XER},
 484                                 initial_cr = CR, expected=e)
 485
 486     def case_cmpli_microwatt(self):
 487         """microwatt 1.bin: cmpli
 488            123ac:   9c 79 8d 2a     cmpli   cr5,0,r13,31132
 489             gpr: 00000000301fc7a7 <- r13
 490             cr : 0000000090215393
 491             xer: so 1 ca 0 32 0 ov 0 32 0
 492
 493         """
 494
 495         lst = ["cmpli 5, 0, 13, 31132"]
 496         initial_regs = [0] * 32
 497         initial_regs[13] = 0x301fc7a7
 498         XER = 0xe00c0000
 499         CR = 0x90215393
 500
 501         e = ExpectedState(pc=4)
 502         e.intregs[13] = 0x301fc7a7
 503         e.crregs[0] = 0x9
 504         e.crregs[2] = 0x2
 505         e.crregs[3] = 0x1
 506         e.crregs[4] = 0x5
 507         e.crregs[5] = 0x5
 508         e.crregs[6] = 0x9
 509         e.crregs[7] = 0x3
 510         e.so = 0x1
 511         e.ov = 0x3
 512         e.ca = 0x3
 513
 514         self.add_case(Program(lst, bigendian), initial_regs,
 515                                 initial_sprs = {'XER': XER},
 516                                 initial_cr = CR, expected=e)
 517
 518     def case_extsb(self):
 519         insns = ["extsb", "extsh", "extsw"]
 520         for i in range(10):
 521             choice = random.choice(insns)
 522             lst = [f"{choice} 3, 1"]
 523             print(lst)
 524             initial_regs = [0] * 32
 525             initial_regs[1] = random.randint(0, (1 << 64)-1)
 526
 527             e = ExpectedState(pc=4)
 528             e.intregs[1] = initial_regs[1]
 529             if choice == "extsb":
 530                 s = ((initial_regs[1] & 0x1000_0000_0000_0080)>>7)&0x1
 531                 if s == 1:
 532                     value = 0xffff_ffff_ffff_ff<<8
 533                 else:
 534                     value = 0x0
 535                 e.intregs[3] = value | (initial_regs[1] & 0xff)
 536             elif choice == "extsh":
 537                 s = ((initial_regs[1] & 0x1000_0000_0000_8000)>>15)&0x1
 538                 if s == 1:
 539                     value = 0xffff_ffff_ffff<<16
 540                 else:
 541                     value = 0x0
 542                 e.intregs[3] = value | (initial_regs[1] & 0xffff)
 543             else:
 544                 s = ((initial_regs[1] & 0x1000_0000_8000_0000)>>31)&0x1
 545                 if s == 1:
 546                     value = 0xffff_ffff<<32
 547                 else:
 548                     value = 0x0
 549                 e.intregs[3] = value | (initial_regs[1] & 0xffff_ffff)
 550
 551             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 552
 553     def case_cmpeqb(self):
 554         lst = ["cmpeqb cr1, 1, 2"]
 555         for i in range(20):
 556             initial_regs = [0] * 32
 557             initial_regs[1] = i
 558             initial_regs[2] = 0x0001030507090b0f
 559
 560             e = ExpectedState(pc=4)
 561             e.intregs[1] = i
 562             e.intregs[2] = 0x1030507090b0f
 563             matlst = [ 0x00, 0x01, 0x03, 0x05, 0x07, 0x09, 0x0b, 0x0f ]
 564             for j in matlst:
 565                 if j == i:
 566                     e.crregs[1] = 0x4
 567
 568             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 569