2 from openpower
.test
.common
import TestAccumulatorBase
3 from openpower
.endian
import bigendian
4 from openpower
.simulator
.program
import Program
5 from openpower
.decoder
.selectable_int
import SelectableInt
6 from openpower
.decoder
.power_enums
import XER_bits
7 from openpower
.decoder
.isa
.caller
import special_sprs
8 from openpower
.test
.state
import ExpectedState
12 class ALUTestCase(TestAccumulatorBase
):
14 def case_1_regression(self
):
16 initial_regs
= [0] * 32
17 initial_regs
[1] = 0xb6a1fc6c8576af91
18 self
.add_case(Program(lst
, bigendian
), initial_regs
)
19 lst
= [f
"subf 3, 1, 2"]
20 initial_regs
= [0] * 32
21 initial_regs
[1] = 0x3d7f3f7ca24bac7b
22 initial_regs
[2] = 0xf6b2ac5e13ee15c2
23 self
.add_case(Program(lst
, bigendian
), initial_regs
)
24 lst
= [f
"subf 3, 1, 2"]
25 initial_regs
= [0] * 32
26 initial_regs
[1] = 0x833652d96c7c0058
27 initial_regs
[2] = 0x1c27ecff8a086c1a
28 self
.add_case(Program(lst
, bigendian
), initial_regs
)
30 initial_regs
= [0] * 32
31 initial_regs
[1] = 0x7f9497aaff900ea0
32 self
.add_case(Program(lst
, bigendian
), initial_regs
)
33 lst
= [f
"add. 3, 1, 2"]
34 initial_regs
= [0] * 32
35 initial_regs
[1] = 0xc523e996a8ff6215
36 initial_regs
[2] = 0xe1e5b9cc9864c4a8
37 self
.add_case(Program(lst
, bigendian
), initial_regs
)
38 lst
= [f
"add 3, 1, 2"]
39 initial_regs
= [0] * 32
40 initial_regs
[1] = 0x2e08ae202742baf8
41 initial_regs
[2] = 0x86c43ece9efe5baa
42 self
.add_case(Program(lst
, bigendian
), initial_regs
)
45 insns
= ["add", "add.", "subf"]
47 choice
= random
.choice(insns
)
48 lst
= [f
"{choice} 3, 1, 2"]
49 initial_regs
= [0] * 32
50 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
51 initial_regs
[2] = random
.randint(0, (1 << 64)-1)
52 self
.add_case(Program(lst
, bigendian
), initial_regs
)
54 def case_addme_ca_0(self
):
55 insns
= ["addme", "addme.", "addmeo", "addmeo."]
57 lst
= [f
"{choice} 6, 16"]
58 for value
in [0x7ffffffff,
60 initial_regs
= [0] * 32
61 initial_regs
[16] = value
63 xer
= SelectableInt(0, 64)
64 xer
[XER_bits
['CA']] = 0
65 initial_sprs
[special_sprs
['XER']] = xer
66 self
.add_case(Program(lst
, bigendian
),
67 initial_regs
, initial_sprs
)
69 def case_addme_ca_1(self
):
70 insns
= ["addme", "addme.", "addmeo", "addmeo."]
72 lst
= [f
"{choice} 6, 16"]
73 for value
in [0x7ffffffff, # fails, bug #476
75 initial_regs
= [0] * 32
76 initial_regs
[16] = value
78 xer
= SelectableInt(0, 64)
79 xer
[XER_bits
['CA']] = 1
80 initial_sprs
[special_sprs
['XER']] = xer
81 self
.add_case(Program(lst
, bigendian
),
82 initial_regs
, initial_sprs
)
84 def case_addme_ca_so_3(self
):
85 """bug where SO does not get passed through to CR0
87 lst
= ["addme. 6, 16"]
88 initial_regs
= [0] * 32
89 initial_regs
[16] = 0x7ffffffff
91 xer
= SelectableInt(0, 64)
92 xer
[XER_bits
['CA']] = 1
93 xer
[XER_bits
['SO']] = 1
94 initial_sprs
[special_sprs
['XER']] = xer
95 self
.add_case(Program(lst
, bigendian
),
96 initial_regs
, initial_sprs
)
99 insns
= ["addze", "addze.", "addzeo", "addzeo."]
101 lst
= [f
"{choice} 6, 16"]
102 initial_regs
= [0] * 32
103 initial_regs
[16] = 0x00ff00ff00ff0080
104 self
.add_case(Program(lst
, bigendian
), initial_regs
)
106 self
.add_case(Program(lst
, bigendian
), initial_regs
)
108 def case_addis_nonzero_r0_regression(self
):
109 lst
= [f
"addis 3, 0, 1"]
111 initial_regs
= [0] * 32
113 e
= ExpectedState(initial_regs
, pc
=4)
114 e
.intregs
[3] = 0x10000
115 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
117 def case_addis_nonzero_r0(self
):
119 imm
= random
.randint(-(1 << 15), (1 << 15)-1)
120 lst
= [f
"addis 3, 0, {imm}"]
122 initial_regs
= [0] * 32
123 initial_regs
[0] = random
.randint(0, (1 << 64)-1)
124 self
.add_case(Program(lst
, bigendian
), initial_regs
)
126 def case_rand_imm(self
):
127 insns
= ["addi", "addis", "subfic"]
129 choice
= random
.choice(insns
)
130 imm
= random
.randint(-(1 << 15), (1 << 15)-1)
131 lst
= [f
"{choice} 3, 1, {imm}"]
133 initial_regs
= [0] * 32
134 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
135 self
.add_case(Program(lst
, bigendian
), initial_regs
)
137 def case_0_adde(self
):
138 lst
= ["adde. 5, 6, 7"]
140 initial_regs
= [0] * 32
141 initial_regs
[6] = random
.randint(0, (1 << 64)-1)
142 initial_regs
[7] = random
.randint(0, (1 << 64)-1)
144 xer
= SelectableInt(0, 64)
145 xer
[XER_bits
['CA']] = 1
146 initial_sprs
[special_sprs
['XER']] = xer
147 self
.add_case(Program(lst
, bigendian
),
148 initial_regs
, initial_sprs
)
151 lst
= ["subf. 1, 6, 7",
153 initial_regs
= [0] * 32
154 initial_regs
[6] = 0x10
155 initial_regs
[7] = 0x05
156 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
159 lst
= ["cmp cr2, 0, 2, 3"]
160 initial_regs
= [0] * 32
161 initial_regs
[2] = 0xffffffffaaaaaaaa
162 initial_regs
[3] = 0x00000000aaaaaaaa
163 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
165 lst
= ["cmp cr2, 0, 4, 5"]
166 initial_regs
= [0] * 32
167 initial_regs
[4] = 0x00000000aaaaaaaa
168 initial_regs
[5] = 0xffffffffaaaaaaaa
169 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
172 lst
= ["cmp cr2, 1, 2, 3"]
173 initial_regs
= [0] * 32
174 initial_regs
[2] = 0xffffffffaaaaaaaa
175 initial_regs
[3] = 0x00000000aaaaaaaa
176 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
178 lst
= ["cmp cr2, 1, 4, 5"]
179 initial_regs
= [0] * 32
180 initial_regs
[4] = 0x00000000aaaaaaaa
181 initial_regs
[5] = 0xffffffffaaaaaaaa
182 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
184 def case_cmpl_microwatt_0(self
):
186 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
187 register_file.vhdl: Reading GPR 11 000000000001C026
188 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
189 cr_file.vhdl: Reading CR 35055050
190 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
193 lst
= ["cmpl 6, 0, 17, 10"]
194 initial_regs
= [0] * 32
195 initial_regs
[0x11] = 0x1c026
196 initial_regs
[0xa] = 0xFEDF3FFF0001C025
200 self
.add_case(Program(lst
, bigendian
), initial_regs
,
201 initial_sprs
= {'XER': XER
},
204 def case_cmpl_microwatt_0_disasm(self
):
205 """microwatt 1.bin: disassembled version
206 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
207 register_file.vhdl: Reading GPR 11 000000000001C026
208 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
209 cr_file.vhdl: Reading CR 35055050
210 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
213 dis
= ["cmpl 6, 0, 17, 10"]
214 lst
= bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
215 initial_regs
= [0] * 32
216 initial_regs
[0x11] = 0x1c026
217 initial_regs
[0xa] = 0xFEDF3FFF0001C025
221 p
= Program(lst
, bigendian
)
222 p
.assembly
= '\n'.join(dis
)+'\n'
223 self
.add_case(p
, initial_regs
,
224 initial_sprs
= {'XER': XER
},
227 def case_cmplw_microwatt_1(self
):
229 10d94: 40 20 96 7c cmplw cr1,r22,r4
230 gpr: 00000000ffff6dc1 <- r4
231 gpr: 0000000000000000 <- r22
234 lst
= ["cmpl 1, 0, 22, 4"]
235 initial_regs
= [0] * 32
236 initial_regs
[4] = 0xffff6dc1
241 self
.add_case(Program(lst
, bigendian
), initial_regs
,
242 initial_sprs
= {'XER': XER
},
245 def case_cmpli_microwatt(self
):
246 """microwatt 1.bin: cmpli
247 123ac: 9c 79 8d 2a cmpli cr5,0,r13,31132
248 gpr: 00000000301fc7a7 <- r13
249 cr : 0000000090215393
250 xer: so 1 ca 0 32 0 ov 0 32 0
254 lst
= ["cmpli 5, 0, 13, 31132"]
255 initial_regs
= [0] * 32
256 initial_regs
[13] = 0x301fc7a7
260 self
.add_case(Program(lst
, bigendian
), initial_regs
,
261 initial_sprs
= {'XER': XER
},
264 def case_extsb(self
):
265 insns
= ["extsb", "extsh", "extsw"]
267 choice
= random
.choice(insns
)
268 lst
= [f
"{choice} 3, 1"]
270 initial_regs
= [0] * 32
271 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
272 self
.add_case(Program(lst
, bigendian
), initial_regs
)
274 def case_cmpeqb(self
):
275 lst
= ["cmpeqb cr1, 1, 2"]
277 initial_regs
= [0] * 32
279 initial_regs
[2] = 0x0001030507090b0f
280 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})