XER regspec_decode_write was not sophisticated enough.
[openpower-isa.git] / src / openpower / test / alu / alu_cases.py
1 import random
2 from openpower.test.common import TestAccumulatorBase
3 from openpower.endian import bigendian
4 from openpower.simulator.program import Program
5 from openpower.decoder.selectable_int import SelectableInt
6 from openpower.decoder.power_enums import XER_bits
7 from openpower.decoder.isa.caller import special_sprs
8 from openpower.test.state import ExpectedState
9 import unittest
10
11
12 class ALUTestCase(TestAccumulatorBase):
13
14 def case_1_regression(self):
15 lst = [f"add. 3, 1, 2"]
16 initial_regs = [0] * 32
17 initial_regs[1] = 0xc523e996a8ff6215
18 initial_regs[2] = 0xe1e5b9cc9864c4a8
19 e = ExpectedState(pc=4)
20 e.intregs[1] = 0xc523e996a8ff6215
21 e.intregs[2] = 0xe1e5b9cc9864c4a8
22 e.intregs[3] = 0xa709a363416426bd
23 e.crregs[0] = 0x8
24 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
25
26 def case_2_regression(self):
27 lst = [f"extsw 3, 1"]
28 initial_regs = [0] * 32
29 initial_regs[1] = 0xb6a1fc6c8576af91
30 e = ExpectedState(pc=4)
31 e.intregs[1] = 0xb6a1fc6c8576af91
32 e.intregs[3] = 0xffffffff8576af91
33 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
34
35 lst = [f"subf 3, 1, 2"]
36 initial_regs = [0] * 32
37 initial_regs[1] = 0x3d7f3f7ca24bac7b
38 initial_regs[2] = 0xf6b2ac5e13ee15c2
39 e = ExpectedState(pc=4)
40 e.intregs[1] = 0x3d7f3f7ca24bac7b
41 e.intregs[2] = 0xf6b2ac5e13ee15c2
42 e.intregs[3] = 0xb9336ce171a26947
43 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
44
45 lst = [f"subf 3, 1, 2"]
46 initial_regs = [0] * 32
47 initial_regs[1] = 0x833652d96c7c0058
48 initial_regs[2] = 0x1c27ecff8a086c1a
49 e = ExpectedState(pc=4)
50 e.intregs[1] = 0x833652d96c7c0058
51 e.intregs[2] = 0x1c27ecff8a086c1a
52 e.intregs[3] = 0x98f19a261d8c6bc2
53 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
54
55 lst = [f"extsb 3, 1"]
56 initial_regs = [0] * 32
57 initial_regs[1] = 0x7f9497aaff900ea0
58 e = ExpectedState(pc=4)
59 e.intregs[1] = 0x7f9497aaff900ea0
60 e.intregs[3] = 0xffffffffffffffa0
61 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
62
63 lst = [f"add 3, 1, 2"]
64 initial_regs = [0] * 32
65 initial_regs[1] = 0x2e08ae202742baf8
66 initial_regs[2] = 0x86c43ece9efe5baa
67 e = ExpectedState(pc=4)
68 e.intregs[1] = 0x2e08ae202742baf8
69 e.intregs[2] = 0x86c43ece9efe5baa
70 e.intregs[3] = 0xb4cceceec64116a2
71 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
72
73 def case_rand(self):
74 insns = ["add", "add.", "subf"]
75 for i in range(40):
76 choice = random.choice(insns)
77 lst = [f"{choice} 3, 1, 2"]
78 initial_regs = [0] * 32
79 initial_regs[1] = random.randint(0, (1 << 64)-1)
80 initial_regs[2] = random.randint(0, (1 << 64)-1)
81 self.add_case(Program(lst, bigendian), initial_regs)
82
83 def case_addme_ca_0(self):
84 insns = ["addme", "addme.", "addmeo", "addmeo."]
85 for choice in insns:
86 lst = [f"{choice} 6, 16"]
87 for value in [0x7ffffffff,
88 0xffff80000]:
89 initial_regs = [0] * 32
90 initial_regs[16] = value
91 initial_sprs = {}
92 xer = SelectableInt(0, 64)
93 xer[XER_bits['CA']] = 0 # input carry is 0 (see test below)
94 initial_sprs[special_sprs['XER']] = xer
95
96 # create expected results. pc should be 4 (one instruction)
97 e = ExpectedState(pc=4)
98 # input value should not be modified
99 e.intregs[16] = value
100 # carry-out should always occur
101 e.ca = 0x3
102 # create output value
103 if value == 0x7ffffffff:
104 e.intregs[6] = 0x7fffffffe
105 else:
106 e.intregs[6] = 0xffff7ffff
107 # CR version needs an expected CR
108 if '.' in choice:
109 e.crregs[0] = 0x4
110 self.add_case(Program(lst, bigendian),
111 initial_regs, initial_sprs,
112 expected=e)
113
114 def case_addme_ca_1(self):
115 insns = ["addme", "addme.", "addmeo", "addmeo."]
116 for choice in insns:
117 lst = [f"{choice} 6, 16"]
118 for value in [0x7ffffffff, # fails, bug #476
119 0xffff80000]:
120 initial_regs = [0] * 32
121 initial_regs[16] = value
122 initial_sprs = {}
123 xer = SelectableInt(0, 64)
124 xer[XER_bits['CA']] = 1 # input carry is 1 (differs from above)
125 initial_sprs[special_sprs['XER']] = xer
126 self.add_case(Program(lst, bigendian),
127 initial_regs, initial_sprs)
128
129 def case_addme_ca_so_4(self):
130 """test of SO being set
131 """
132 lst = ["addmeo. 6, 16"]
133 initial_regs = [0] * 32
134 initial_regs[16] = 0x7fffffffffffffff
135 initial_sprs = {}
136 xer = SelectableInt(0, 64)
137 xer[XER_bits['CA']] = 1
138 initial_sprs[special_sprs['XER']] = xer
139 self.add_case(Program(lst, bigendian),
140 initial_regs, initial_sprs)
141
142 def case_addme_ca_so_3(self):
143 """bug where SO does not get passed through to CR0
144 """
145 lst = ["addme. 6, 16"]
146 initial_regs = [0] * 32
147 initial_regs[16] = 0x7ffffffff
148 initial_sprs = {}
149 xer = SelectableInt(0, 64)
150 xer[XER_bits['CA']] = 1
151 xer[XER_bits['SO']] = 1
152 initial_sprs[special_sprs['XER']] = xer
153 self.add_case(Program(lst, bigendian),
154 initial_regs, initial_sprs)
155
156 def case_addze(self):
157 insns = ["addze", "addze.", "addzeo", "addzeo."]
158 for choice in insns:
159 lst = [f"{choice} 6, 16"]
160 initial_regs = [0] * 32
161 initial_regs[16] = 0x00ff00ff00ff0080
162 if choice == "addze":
163 e = ExpectedState(pc=4)
164 e.intregs[6] = 0xff00ff00ff0080
165 e.intregs[16] = 0xff00ff00ff0080
166 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
167 else:
168 self.add_case(Program(lst, bigendian), initial_regs)
169
170 def case_addis_nonzero_r0_regression(self):
171 lst = [f"addis 3, 0, 1"]
172 print(lst)
173 initial_regs = [0] * 32
174 initial_regs[0] = 5
175 e = ExpectedState(initial_regs, pc=4)
176 e.intregs[3] = 0x10000
177 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
178
179 def case_addis_nonzero_r0(self):
180 for i in range(10):
181 imm = random.randint(-(1 << 15), (1 << 15)-1)
182 lst = [f"addis 3, 0, {imm}"]
183 print(lst)
184 initial_regs = [0] * 32
185 initial_regs[0] = random.randint(0, (1 << 64)-1)
186 self.add_case(Program(lst, bigendian), initial_regs)
187
188 def case_rand_imm(self):
189 insns = ["addi", "addis", "subfic"]
190 for i in range(10):
191 choice = random.choice(insns)
192 imm = random.randint(-(1 << 15), (1 << 15)-1)
193 lst = [f"{choice} 3, 1, {imm}"]
194 print(lst)
195 initial_regs = [0] * 32
196 initial_regs[1] = random.randint(0, (1 << 64)-1)
197 self.add_case(Program(lst, bigendian), initial_regs)
198
199 def case_0_adde(self):
200 lst = ["adde. 5, 6, 7"]
201 for i in range(10):
202 initial_regs = [0] * 32
203 initial_regs[6] = random.randint(0, (1 << 64)-1)
204 initial_regs[7] = random.randint(0, (1 << 64)-1)
205 initial_sprs = {}
206 xer = SelectableInt(0, 64)
207 xer[XER_bits['CA']] = 1
208 initial_sprs[special_sprs['XER']] = xer
209 self.add_case(Program(lst, bigendian),
210 initial_regs, initial_sprs)
211
212 def case_cmp(self):
213 lst = ["subf. 1, 6, 7",
214 "cmp cr2, 1, 6, 7"]
215 initial_regs = [0] * 32
216 initial_regs[6] = 0x10
217 initial_regs[7] = 0x05
218 self.add_case(Program(lst, bigendian), initial_regs, {})
219
220 def case_cmp2(self):
221 lst = ["cmp cr2, 0, 2, 3"]
222 initial_regs = [0] * 32
223 initial_regs[2] = 0xffffffffaaaaaaaa
224 initial_regs[3] = 0x00000000aaaaaaaa
225 self.add_case(Program(lst, bigendian), initial_regs, {})
226
227 lst = ["cmp cr2, 0, 4, 5"]
228 initial_regs = [0] * 32
229 initial_regs[4] = 0x00000000aaaaaaaa
230 initial_regs[5] = 0xffffffffaaaaaaaa
231 self.add_case(Program(lst, bigendian), initial_regs, {})
232
233 def case_cmp3(self):
234 lst = ["cmp cr2, 1, 2, 3"]
235 initial_regs = [0] * 32
236 initial_regs[2] = 0xffffffffaaaaaaaa
237 initial_regs[3] = 0x00000000aaaaaaaa
238 self.add_case(Program(lst, bigendian), initial_regs, {})
239
240 lst = ["cmp cr2, 1, 4, 5"]
241 initial_regs = [0] * 32
242 initial_regs[4] = 0x00000000aaaaaaaa
243 initial_regs[5] = 0xffffffffaaaaaaaa
244 self.add_case(Program(lst, bigendian), initial_regs, {})
245
246 def case_cmpl_microwatt_0(self):
247 """microwatt 1.bin:
248 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
249 register_file.vhdl: Reading GPR 11 000000000001C026
250 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
251 cr_file.vhdl: Reading CR 35055050
252 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
253 """
254
255 lst = ["cmpl 6, 0, 17, 10"]
256 initial_regs = [0] * 32
257 initial_regs[0x11] = 0x1c026
258 initial_regs[0xa] = 0xFEDF3FFF0001C025
259 XER = 0xe00c0000
260 CR = 0x35055050
261
262 self.add_case(Program(lst, bigendian), initial_regs,
263 initial_sprs = {'XER': XER},
264 initial_cr = CR)
265
266 def case_cmpl_microwatt_0_disasm(self):
267 """microwatt 1.bin: disassembled version
268 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
269 register_file.vhdl: Reading GPR 11 000000000001C026
270 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
271 cr_file.vhdl: Reading CR 35055050
272 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
273 """
274
275 dis = ["cmpl 6, 0, 17, 10"]
276 lst = bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
277 initial_regs = [0] * 32
278 initial_regs[0x11] = 0x1c026
279 initial_regs[0xa] = 0xFEDF3FFF0001C025
280 XER = 0xe00c0000
281 CR = 0x35055050
282
283 p = Program(lst, bigendian)
284 p.assembly = '\n'.join(dis)+'\n'
285 self.add_case(p, initial_regs,
286 initial_sprs = {'XER': XER},
287 initial_cr = CR)
288
289 def case_cmplw_microwatt_1(self):
290 """microwatt 1.bin:
291 10d94: 40 20 96 7c cmplw cr1,r22,r4
292 gpr: 00000000ffff6dc1 <- r4
293 gpr: 0000000000000000 <- r22
294 """
295
296 lst = ["cmpl 1, 0, 22, 4"]
297 initial_regs = [0] * 32
298 initial_regs[4] = 0xffff6dc1
299 initial_regs[22] = 0
300 XER = 0xe00c0000
301 CR = 0x50759999
302
303 self.add_case(Program(lst, bigendian), initial_regs,
304 initial_sprs = {'XER': XER},
305 initial_cr = CR)
306
307 def case_cmpli_microwatt(self):
308 """microwatt 1.bin: cmpli
309 123ac: 9c 79 8d 2a cmpli cr5,0,r13,31132
310 gpr: 00000000301fc7a7 <- r13
311 cr : 0000000090215393
312 xer: so 1 ca 0 32 0 ov 0 32 0
313
314 """
315
316 lst = ["cmpli 5, 0, 13, 31132"]
317 initial_regs = [0] * 32
318 initial_regs[13] = 0x301fc7a7
319 XER = 0xe00c0000
320 CR = 0x90215393
321
322 self.add_case(Program(lst, bigendian), initial_regs,
323 initial_sprs = {'XER': XER},
324 initial_cr = CR)
325
326 def case_extsb(self):
327 insns = ["extsb", "extsh", "extsw"]
328 for i in range(10):
329 choice = random.choice(insns)
330 lst = [f"{choice} 3, 1"]
331 print(lst)
332 initial_regs = [0] * 32
333 initial_regs[1] = random.randint(0, (1 << 64)-1)
334 self.add_case(Program(lst, bigendian), initial_regs)
335
336 def case_cmpeqb(self):
337 lst = ["cmpeqb cr1, 1, 2"]
338 for i in range(20):
339 initial_regs = [0] * 32
340 initial_regs[1] = i
341 initial_regs[2] = 0x0001030507090b0f
342 self.add_case(Program(lst, bigendian), initial_regs, {})
343