https://bugs.libre-soc.org/show_bug.cgi?id=730#c27
[openpower-isa.git] / src / openpower / test / alu / alu_cases.py
1 import random
2 from openpower.test.common import TestAccumulatorBase
3 from openpower.endian import bigendian
4 from openpower.simulator.program import Program
5 from openpower.decoder.selectable_int import SelectableInt
6 from openpower.decoder.power_enums import XER_bits
7 from openpower.decoder.isa.caller import special_sprs
8 from openpower.test.state import ExpectedState
9 import unittest
10
11
12 class ALUTestCase(TestAccumulatorBase):
13
14 def case_1_regression(self):
15 lst = [f"extsw 3, 1"]
16 initial_regs = [0] * 32
17 initial_regs[1] = 0xb6a1fc6c8576af91
18 e = ExpectedState(pc=4)
19 e.intregs[1] = 0xb6a1fc6c8576af91
20 e.intregs[3] = 0xffffffff8576af91
21 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
22 lst = [f"subf 3, 1, 2"]
23 initial_regs = [0] * 32
24 initial_regs[1] = 0x3d7f3f7ca24bac7b
25 initial_regs[2] = 0xf6b2ac5e13ee15c2
26 e = ExpectedState(pc=4)
27 e.intregs[1] = 0x3d7f3f7ca24bac7b
28 e.intregs[2] = 0xf6b2ac5e13ee15c2
29 e.intregs[3] = 0xb9336ce171a26947
30 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
31 lst = [f"subf 3, 1, 2"]
32 initial_regs = [0] * 32
33 initial_regs[1] = 0x833652d96c7c0058
34 initial_regs[2] = 0x1c27ecff8a086c1a
35 e = ExpectedState(pc=4)
36 e.intregs[1] = 0x833652d96c7c0058
37 e.intregs[2] = 0x1c27ecff8a086c1a
38 e.intregs[3] = 0x98f19a261d8c6bc2
39 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
40 lst = [f"extsb 3, 1"]
41 initial_regs = [0] * 32
42 initial_regs[1] = 0x7f9497aaff900ea0
43 e = ExpectedState(pc=4)
44 e.intregs[1] = 0x7f9497aaff900ea0
45 e.intregs[3] = 0xffffffffffffffa0
46 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
47 lst = [f"add. 3, 1, 2"]
48 initial_regs = [0] * 32
49 initial_regs[1] = 0xc523e996a8ff6215
50 initial_regs[2] = 0xe1e5b9cc9864c4a8
51 e = ExpectedState(pc=4)
52 e.intregs[1] = 0xc523e996a8ff6215
53 e.intregs[2] = 0xe1e5b9cc9864c4a8
54 e.intregs[3] = 0xa709a363416426bd
55 e.crregs[0] = 0x8
56 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
57 lst = [f"add 3, 1, 2"]
58 initial_regs = [0] * 32
59 initial_regs[1] = 0x2e08ae202742baf8
60 initial_regs[2] = 0x86c43ece9efe5baa
61 e = ExpectedState(pc=4)
62 e.intregs[1] = 0x2e08ae202742baf8
63 e.intregs[2] = 0x86c43ece9efe5baa
64 e.intregs[3] = 0xb4cceceec64116a2
65 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
66
67 def cse_rand(self):
68 insns = ["add", "add.", "subf"]
69 for i in range(40):
70 choice = random.choice(insns)
71 lst = [f"{choice} 3, 1, 2"]
72 initial_regs = [0] * 32
73 initial_regs[1] = random.randint(0, (1 << 64)-1)
74 initial_regs[2] = random.randint(0, (1 << 64)-1)
75 self.add_case(Program(lst, bigendian), initial_regs)
76
77 def cse_addme_ca_0(self):
78 insns = ["addme", "addme.", "addmeo", "addmeo."]
79 for choice in insns:
80 lst = [f"{choice} 6, 16"]
81 for value in [0x7ffffffff,
82 0xffff80000]:
83 initial_regs = [0] * 32
84 initial_regs[16] = value
85 initial_sprs = {}
86 xer = SelectableInt(0, 64)
87 xer[XER_bits['CA']] = 0
88 initial_sprs[special_sprs['XER']] = xer
89 self.add_case(Program(lst, bigendian),
90 initial_regs, initial_sprs)
91
92 def cse_addme_ca_1(self):
93 insns = ["addme", "addme.", "addmeo", "addmeo."]
94 for choice in insns:
95 lst = [f"{choice} 6, 16"]
96 for value in [0x7ffffffff, # fails, bug #476
97 0xffff80000]:
98 initial_regs = [0] * 32
99 initial_regs[16] = value
100 initial_sprs = {}
101 xer = SelectableInt(0, 64)
102 xer[XER_bits['CA']] = 1
103 initial_sprs[special_sprs['XER']] = xer
104 self.add_case(Program(lst, bigendian),
105 initial_regs, initial_sprs)
106
107 def cse_addme_ca_so_3(self):
108 """bug where SO does not get passed through to CR0
109 """
110 lst = ["addme. 6, 16"]
111 initial_regs = [0] * 32
112 initial_regs[16] = 0x7ffffffff
113 initial_sprs = {}
114 xer = SelectableInt(0, 64)
115 xer[XER_bits['CA']] = 1
116 xer[XER_bits['SO']] = 1
117 initial_sprs[special_sprs['XER']] = xer
118 self.add_case(Program(lst, bigendian),
119 initial_regs, initial_sprs)
120
121 def cse_addze(self):
122 insns = ["addze", "addze.", "addzeo", "addzeo."]
123 for choice in insns:
124 lst = [f"{choice} 6, 16"]
125 initial_regs = [0] * 32
126 initial_regs[16] = 0x00ff00ff00ff0080
127 if choice == "addze":
128 e = ExpectedState(pc=4)
129 e.intregs[6] = 0xff00ff00ff0080
130 e.intregs[16] = 0xff00ff00ff0080
131 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
132 else:
133 self.add_case(Program(lst, bigendian), initial_regs)
134
135 def cse_addis_nonzero_r0_regression(self):
136 lst = [f"addis 3, 0, 1"]
137 print(lst)
138 initial_regs = [0] * 32
139 initial_regs[0] = 5
140 e = ExpectedState(initial_regs, pc=4)
141 e.intregs[3] = 0x10000
142 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
143
144 def cse_addis_nonzero_r0(self):
145 for i in range(10):
146 imm = random.randint(-(1 << 15), (1 << 15)-1)
147 lst = [f"addis 3, 0, {imm}"]
148 print(lst)
149 initial_regs = [0] * 32
150 initial_regs[0] = random.randint(0, (1 << 64)-1)
151 self.add_case(Program(lst, bigendian), initial_regs)
152
153 def cse_rand_imm(self):
154 insns = ["addi", "addis", "subfic"]
155 for i in range(10):
156 choice = random.choice(insns)
157 imm = random.randint(-(1 << 15), (1 << 15)-1)
158 lst = [f"{choice} 3, 1, {imm}"]
159 print(lst)
160 initial_regs = [0] * 32
161 initial_regs[1] = random.randint(0, (1 << 64)-1)
162 self.add_case(Program(lst, bigendian), initial_regs)
163
164 def cse_0_adde(self):
165 lst = ["adde. 5, 6, 7"]
166 for i in range(10):
167 initial_regs = [0] * 32
168 initial_regs[6] = random.randint(0, (1 << 64)-1)
169 initial_regs[7] = random.randint(0, (1 << 64)-1)
170 initial_sprs = {}
171 xer = SelectableInt(0, 64)
172 xer[XER_bits['CA']] = 1
173 initial_sprs[special_sprs['XER']] = xer
174 self.add_case(Program(lst, bigendian),
175 initial_regs, initial_sprs)
176
177 def cse_cmp(self):
178 lst = ["subf. 1, 6, 7",
179 "cmp cr2, 1, 6, 7"]
180 initial_regs = [0] * 32
181 initial_regs[6] = 0x10
182 initial_regs[7] = 0x05
183 self.add_case(Program(lst, bigendian), initial_regs, {})
184
185 def cse_cmp2(self):
186 lst = ["cmp cr2, 0, 2, 3"]
187 initial_regs = [0] * 32
188 initial_regs[2] = 0xffffffffaaaaaaaa
189 initial_regs[3] = 0x00000000aaaaaaaa
190 self.add_case(Program(lst, bigendian), initial_regs, {})
191
192 lst = ["cmp cr2, 0, 4, 5"]
193 initial_regs = [0] * 32
194 initial_regs[4] = 0x00000000aaaaaaaa
195 initial_regs[5] = 0xffffffffaaaaaaaa
196 self.add_case(Program(lst, bigendian), initial_regs, {})
197
198 def cse_cmp3(self):
199 lst = ["cmp cr2, 1, 2, 3"]
200 initial_regs = [0] * 32
201 initial_regs[2] = 0xffffffffaaaaaaaa
202 initial_regs[3] = 0x00000000aaaaaaaa
203 self.add_case(Program(lst, bigendian), initial_regs, {})
204
205 lst = ["cmp cr2, 1, 4, 5"]
206 initial_regs = [0] * 32
207 initial_regs[4] = 0x00000000aaaaaaaa
208 initial_regs[5] = 0xffffffffaaaaaaaa
209 self.add_case(Program(lst, bigendian), initial_regs, {})
210
211 def cse_cmpl_microwatt_0(self):
212 """microwatt 1.bin:
213 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
214 register_file.vhdl: Reading GPR 11 000000000001C026
215 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
216 cr_file.vhdl: Reading CR 35055050
217 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
218 """
219
220 lst = ["cmpl 6, 0, 17, 10"]
221 initial_regs = [0] * 32
222 initial_regs[0x11] = 0x1c026
223 initial_regs[0xa] = 0xFEDF3FFF0001C025
224 XER = 0xe00c0000
225 CR = 0x35055050
226
227 self.add_case(Program(lst, bigendian), initial_regs,
228 initial_sprs = {'XER': XER},
229 initial_cr = CR)
230
231 def cse_cmpl_microwatt_0_disasm(self):
232 """microwatt 1.bin: disassembled version
233 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
234 register_file.vhdl: Reading GPR 11 000000000001C026
235 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
236 cr_file.vhdl: Reading CR 35055050
237 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
238 """
239
240 dis = ["cmpl 6, 0, 17, 10"]
241 lst = bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
242 initial_regs = [0] * 32
243 initial_regs[0x11] = 0x1c026
244 initial_regs[0xa] = 0xFEDF3FFF0001C025
245 XER = 0xe00c0000
246 CR = 0x35055050
247
248 p = Program(lst, bigendian)
249 p.assembly = '\n'.join(dis)+'\n'
250 self.add_case(p, initial_regs,
251 initial_sprs = {'XER': XER},
252 initial_cr = CR)
253
254 def cse_cmplw_microwatt_1(self):
255 """microwatt 1.bin:
256 10d94: 40 20 96 7c cmplw cr1,r22,r4
257 gpr: 00000000ffff6dc1 <- r4
258 gpr: 0000000000000000 <- r22
259 """
260
261 lst = ["cmpl 1, 0, 22, 4"]
262 initial_regs = [0] * 32
263 initial_regs[4] = 0xffff6dc1
264 initial_regs[22] = 0
265 XER = 0xe00c0000
266 CR = 0x50759999
267
268 self.add_case(Program(lst, bigendian), initial_regs,
269 initial_sprs = {'XER': XER},
270 initial_cr = CR)
271
272 def cse_cmpli_microwatt(self):
273 """microwatt 1.bin: cmpli
274 123ac: 9c 79 8d 2a cmpli cr5,0,r13,31132
275 gpr: 00000000301fc7a7 <- r13
276 cr : 0000000090215393
277 xer: so 1 ca 0 32 0 ov 0 32 0
278
279 """
280
281 lst = ["cmpli 5, 0, 13, 31132"]
282 initial_regs = [0] * 32
283 initial_regs[13] = 0x301fc7a7
284 XER = 0xe00c0000
285 CR = 0x90215393
286
287 self.add_case(Program(lst, bigendian), initial_regs,
288 initial_sprs = {'XER': XER},
289 initial_cr = CR)
290
291 def cse_extsb(self):
292 insns = ["extsb", "extsh", "extsw"]
293 for i in range(10):
294 choice = random.choice(insns)
295 lst = [f"{choice} 3, 1"]
296 print(lst)
297 initial_regs = [0] * 32
298 initial_regs[1] = random.randint(0, (1 << 64)-1)
299 self.add_case(Program(lst, bigendian), initial_regs)
300
301 def cse_cmpeqb(self):
302 lst = ["cmpeqb cr1, 1, 2"]
303 for i in range(20):
304 initial_regs = [0] * 32
305 initial_regs[1] = i
306 initial_regs[2] = 0x0001030507090b0f
307 self.add_case(Program(lst, bigendian), initial_regs, {})
308