2 from openpower
.test
.common
import TestAccumulatorBase
3 from openpower
.endian
import bigendian
4 from openpower
.simulator
.program
import Program
5 from openpower
.decoder
.selectable_int
import SelectableInt
6 from openpower
.decoder
.power_enums
import XER_bits
7 from openpower
.decoder
.isa
.caller
import special_sprs
8 from openpower
.test
.state
import ExpectedState
12 class ALUTestCase(TestAccumulatorBase
):
14 def case_1_regression(self
):
16 initial_regs
= [0] * 32
17 initial_regs
[1] = 0xb6a1fc6c8576af91
18 e
= ExpectedState(pc
=4)
19 e
.intregs
[1] = 0xb6a1fc6c8576af91
20 e
.intregs
[3] = 0xffffffff8576af91
21 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
23 lst
= [f
"subf 3, 1, 2"]
24 initial_regs
= [0] * 32
25 initial_regs
[1] = 0x3d7f3f7ca24bac7b
26 initial_regs
[2] = 0xf6b2ac5e13ee15c2
27 e
= ExpectedState(pc
=4)
28 e
.intregs
[1] = 0x3d7f3f7ca24bac7b
29 e
.intregs
[2] = 0xf6b2ac5e13ee15c2
30 e
.intregs
[3] = 0xb9336ce171a26947
31 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
33 lst
= [f
"subf 3, 1, 2"]
34 initial_regs
= [0] * 32
35 initial_regs
[1] = 0x833652d96c7c0058
36 initial_regs
[2] = 0x1c27ecff8a086c1a
37 e
= ExpectedState(pc
=4)
38 e
.intregs
[1] = 0x833652d96c7c0058
39 e
.intregs
[2] = 0x1c27ecff8a086c1a
40 e
.intregs
[3] = 0x98f19a261d8c6bc2
41 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
44 initial_regs
= [0] * 32
45 initial_regs
[1] = 0x7f9497aaff900ea0
46 e
= ExpectedState(pc
=4)
47 e
.intregs
[1] = 0x7f9497aaff900ea0
48 e
.intregs
[3] = 0xffffffffffffffa0
49 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
51 lst
= [f
"add. 3, 1, 2"]
52 initial_regs
= [0] * 32
53 initial_regs
[1] = 0xc523e996a8ff6215
54 initial_regs
[2] = 0xe1e5b9cc9864c4a8
55 e
= ExpectedState(pc
=4)
56 e
.intregs
[1] = 0xc523e996a8ff6215
57 e
.intregs
[2] = 0xe1e5b9cc9864c4a8
58 e
.intregs
[3] = 0xa709a363416426bd
60 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
62 lst
= [f
"add 3, 1, 2"]
63 initial_regs
= [0] * 32
64 initial_regs
[1] = 0x2e08ae202742baf8
65 initial_regs
[2] = 0x86c43ece9efe5baa
66 e
= ExpectedState(pc
=4)
67 e
.intregs
[1] = 0x2e08ae202742baf8
68 e
.intregs
[2] = 0x86c43ece9efe5baa
69 e
.intregs
[3] = 0xb4cceceec64116a2
70 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
73 insns
= ["add", "add.", "subf"]
75 choice
= random
.choice(insns
)
76 lst
= [f
"{choice} 3, 1, 2"]
77 initial_regs
= [0] * 32
78 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
79 initial_regs
[2] = random
.randint(0, (1 << 64)-1)
80 self
.add_case(Program(lst
, bigendian
), initial_regs
)
82 def case_addme_ca_0(self
):
83 insns
= ["addme", "addme.", "addmeo", "addmeo."]
85 lst
= [f
"{choice} 6, 16"]
86 for value
in [0x7ffffffff,
88 initial_regs
= [0] * 32
89 initial_regs
[16] = value
91 xer
= SelectableInt(0, 64)
92 xer
[XER_bits
['CA']] = 0
93 initial_sprs
[special_sprs
['XER']] = xer
94 self
.add_case(Program(lst
, bigendian
),
95 initial_regs
, initial_sprs
)
97 def case_addme_ca_1(self
):
98 insns
= ["addme", "addme.", "addmeo", "addmeo."]
100 lst
= [f
"{choice} 6, 16"]
101 for value
in [0x7ffffffff, # fails, bug #476
103 initial_regs
= [0] * 32
104 initial_regs
[16] = value
106 xer
= SelectableInt(0, 64)
107 xer
[XER_bits
['CA']] = 1
108 initial_sprs
[special_sprs
['XER']] = xer
109 self
.add_case(Program(lst
, bigendian
),
110 initial_regs
, initial_sprs
)
112 def case_addme_ca_so_3(self
):
113 """bug where SO does not get passed through to CR0
115 lst
= ["addme. 6, 16"]
116 initial_regs
= [0] * 32
117 initial_regs
[16] = 0x7ffffffff
119 xer
= SelectableInt(0, 64)
120 xer
[XER_bits
['CA']] = 1
121 xer
[XER_bits
['SO']] = 1
122 initial_sprs
[special_sprs
['XER']] = xer
123 self
.add_case(Program(lst
, bigendian
),
124 initial_regs
, initial_sprs
)
126 def case_addze(self
):
127 insns
= ["addze", "addze.", "addzeo", "addzeo."]
129 lst
= [f
"{choice} 6, 16"]
130 initial_regs
= [0] * 32
131 initial_regs
[16] = 0x00ff00ff00ff0080
132 if choice
== "addze":
133 e
= ExpectedState(pc
=4)
134 e
.intregs
[6] = 0xff00ff00ff0080
135 e
.intregs
[16] = 0xff00ff00ff0080
136 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
138 self
.add_case(Program(lst
, bigendian
), initial_regs
)
140 def case_addis_nonzero_r0_regression(self
):
141 lst
= [f
"addis 3, 0, 1"]
143 initial_regs
= [0] * 32
145 e
= ExpectedState(initial_regs
, pc
=4)
146 e
.intregs
[3] = 0x10000
147 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
149 def case_addis_nonzero_r0(self
):
151 imm
= random
.randint(-(1 << 15), (1 << 15)-1)
152 lst
= [f
"addis 3, 0, {imm}"]
154 initial_regs
= [0] * 32
155 initial_regs
[0] = random
.randint(0, (1 << 64)-1)
156 self
.add_case(Program(lst
, bigendian
), initial_regs
)
158 def case_rand_imm(self
):
159 insns
= ["addi", "addis", "subfic"]
161 choice
= random
.choice(insns
)
162 imm
= random
.randint(-(1 << 15), (1 << 15)-1)
163 lst
= [f
"{choice} 3, 1, {imm}"]
165 initial_regs
= [0] * 32
166 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
167 self
.add_case(Program(lst
, bigendian
), initial_regs
)
169 def case_0_adde(self
):
170 lst
= ["adde. 5, 6, 7"]
172 initial_regs
= [0] * 32
173 initial_regs
[6] = random
.randint(0, (1 << 64)-1)
174 initial_regs
[7] = random
.randint(0, (1 << 64)-1)
176 xer
= SelectableInt(0, 64)
177 xer
[XER_bits
['CA']] = 1
178 initial_sprs
[special_sprs
['XER']] = xer
179 self
.add_case(Program(lst
, bigendian
),
180 initial_regs
, initial_sprs
)
183 lst
= ["subf. 1, 6, 7",
185 initial_regs
= [0] * 32
186 initial_regs
[6] = 0x10
187 initial_regs
[7] = 0x05
188 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
191 lst
= ["cmp cr2, 0, 2, 3"]
192 initial_regs
= [0] * 32
193 initial_regs
[2] = 0xffffffffaaaaaaaa
194 initial_regs
[3] = 0x00000000aaaaaaaa
195 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
197 lst
= ["cmp cr2, 0, 4, 5"]
198 initial_regs
= [0] * 32
199 initial_regs
[4] = 0x00000000aaaaaaaa
200 initial_regs
[5] = 0xffffffffaaaaaaaa
201 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
204 lst
= ["cmp cr2, 1, 2, 3"]
205 initial_regs
= [0] * 32
206 initial_regs
[2] = 0xffffffffaaaaaaaa
207 initial_regs
[3] = 0x00000000aaaaaaaa
208 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
210 lst
= ["cmp cr2, 1, 4, 5"]
211 initial_regs
= [0] * 32
212 initial_regs
[4] = 0x00000000aaaaaaaa
213 initial_regs
[5] = 0xffffffffaaaaaaaa
214 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
216 def case_cmpl_microwatt_0(self
):
218 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
219 register_file.vhdl: Reading GPR 11 000000000001C026
220 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
221 cr_file.vhdl: Reading CR 35055050
222 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
225 lst
= ["cmpl 6, 0, 17, 10"]
226 initial_regs
= [0] * 32
227 initial_regs
[0x11] = 0x1c026
228 initial_regs
[0xa] = 0xFEDF3FFF0001C025
232 self
.add_case(Program(lst
, bigendian
), initial_regs
,
233 initial_sprs
= {'XER': XER
},
236 def case_cmpl_microwatt_0_disasm(self
):
237 """microwatt 1.bin: disassembled version
238 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
239 register_file.vhdl: Reading GPR 11 000000000001C026
240 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
241 cr_file.vhdl: Reading CR 35055050
242 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
245 dis
= ["cmpl 6, 0, 17, 10"]
246 lst
= bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
247 initial_regs
= [0] * 32
248 initial_regs
[0x11] = 0x1c026
249 initial_regs
[0xa] = 0xFEDF3FFF0001C025
253 p
= Program(lst
, bigendian
)
254 p
.assembly
= '\n'.join(dis
)+'\n'
255 self
.add_case(p
, initial_regs
,
256 initial_sprs
= {'XER': XER
},
259 def case_cmplw_microwatt_1(self
):
261 10d94: 40 20 96 7c cmplw cr1,r22,r4
262 gpr: 00000000ffff6dc1 <- r4
263 gpr: 0000000000000000 <- r22
266 lst
= ["cmpl 1, 0, 22, 4"]
267 initial_regs
= [0] * 32
268 initial_regs
[4] = 0xffff6dc1
273 self
.add_case(Program(lst
, bigendian
), initial_regs
,
274 initial_sprs
= {'XER': XER
},
277 def case_cmpli_microwatt(self
):
278 """microwatt 1.bin: cmpli
279 123ac: 9c 79 8d 2a cmpli cr5,0,r13,31132
280 gpr: 00000000301fc7a7 <- r13
281 cr : 0000000090215393
282 xer: so 1 ca 0 32 0 ov 0 32 0
286 lst
= ["cmpli 5, 0, 13, 31132"]
287 initial_regs
= [0] * 32
288 initial_regs
[13] = 0x301fc7a7
292 self
.add_case(Program(lst
, bigendian
), initial_regs
,
293 initial_sprs
= {'XER': XER
},
296 def case_extsb(self
):
297 insns
= ["extsb", "extsh", "extsw"]
299 choice
= random
.choice(insns
)
300 lst
= [f
"{choice} 3, 1"]
302 initial_regs
= [0] * 32
303 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
304 self
.add_case(Program(lst
, bigendian
), initial_regs
)
306 def case_cmpeqb(self
):
307 lst
= ["cmpeqb cr1, 1, 2"]
309 initial_regs
= [0] * 32
311 initial_regs
[2] = 0x0001030507090b0f
312 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})