src/openpower/test/alu/alu_cases.py

   1 import random
   2 from openpower.test.common import TestAccumulatorBase
   3 from openpower.endian import bigendian
   4 from openpower.simulator.program import Program
   5 from openpower.decoder.selectable_int import SelectableInt
   6 from openpower.decoder.power_enums import XER_bits
   7 from openpower.decoder.isa.caller import special_sprs
   8 from openpower.test.state import ExpectedState
   9 import unittest
  10
  11
  12 class ALUTestCase(TestAccumulatorBase):
  13
  14     def case_1_regression(self):
  15         lst = [f"add. 3, 1, 2"]
  16         initial_regs = [0] * 32
  17         initial_regs[1] = 0xc523e996a8ff6215
  18         initial_regs[2] = 0xe1e5b9cc9864c4a8
  19         e = ExpectedState(pc=4)
  20         e.intregs[1] = 0xc523e996a8ff6215
  21         e.intregs[2] = 0xe1e5b9cc9864c4a8
  22         e.intregs[3] = 0xa709a363416426bd
  23         e.crregs[0] = 0x8
  24         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  25
  26     def case_2_regression(self):
  27         lst = [f"extsw 3, 1"]
  28         initial_regs = [0] * 32
  29         initial_regs[1] = 0xb6a1fc6c8576af91
  30         e = ExpectedState(pc=4)
  31         e.intregs[1] = 0xb6a1fc6c8576af91
  32         e.intregs[3] = 0xffffffff8576af91
  33         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  34
  35         lst = [f"subf 3, 1, 2"]
  36         initial_regs = [0] * 32
  37         initial_regs[1] = 0x3d7f3f7ca24bac7b
  38         initial_regs[2] = 0xf6b2ac5e13ee15c2
  39         e = ExpectedState(pc=4)
  40         e.intregs[1] = 0x3d7f3f7ca24bac7b
  41         e.intregs[2] = 0xf6b2ac5e13ee15c2
  42         e.intregs[3] = 0xb9336ce171a26947
  43         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  44
  45         lst = [f"subf 3, 1, 2"]
  46         initial_regs = [0] * 32
  47         initial_regs[1] = 0x833652d96c7c0058
  48         initial_regs[2] = 0x1c27ecff8a086c1a
  49         e = ExpectedState(pc=4)
  50         e.intregs[1] = 0x833652d96c7c0058
  51         e.intregs[2] = 0x1c27ecff8a086c1a
  52         e.intregs[3] = 0x98f19a261d8c6bc2
  53         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  54
  55         lst = [f"extsb 3, 1"]
  56         initial_regs = [0] * 32
  57         initial_regs[1] = 0x7f9497aaff900ea0
  58         e = ExpectedState(pc=4)
  59         e.intregs[1] = 0x7f9497aaff900ea0
  60         e.intregs[3] = 0xffffffffffffffa0
  61         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  62
  63         lst = [f"add 3, 1, 2"]
  64         initial_regs = [0] * 32
  65         initial_regs[1] = 0x2e08ae202742baf8
  66         initial_regs[2] = 0x86c43ece9efe5baa
  67         e = ExpectedState(pc=4)
  68         e.intregs[1] = 0x2e08ae202742baf8
  69         e.intregs[2] = 0x86c43ece9efe5baa
  70         e.intregs[3] = 0xb4cceceec64116a2
  71         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  72
  73     def case_rand(self):
  74         insns = ["add", "add.", "subf"]
  75         for i in range(40):
  76             choice = random.choice(insns)
  77             lst = [f"{choice} 3, 1, 2"]
  78             initial_regs = [0] * 32
  79             initial_regs[1] = random.randint(0, (1 << 64)-1)
  80             initial_regs[2] = random.randint(0, (1 << 64)-1)
  81             self.add_case(Program(lst, bigendian), initial_regs)
  82
  83     def case_addme_ca_0(self):
  84         insns = ["addme", "addme.", "addmeo", "addmeo."]
  85         for choice in insns:
  86             lst = [f"{choice} 6, 16"]
  87             for value in [0x7ffffffff,
  88                           0xffff80000]:
  89                 initial_regs = [0] * 32
  90                 initial_regs[16] = value
  91                 initial_sprs = {}
  92                 xer = SelectableInt(0, 64)
  93                 xer[XER_bits['CA']] = 0  # input carry is 0 (see test below)
  94                 initial_sprs[special_sprs['XER']] = xer
  95
  96                 # create expected results.  pc should be 4 (one instruction)
  97                 e = ExpectedState(pc=4)
  98                 # input value should not be modified
  99                 e.intregs[16] = value
 100                 # carry-out should always occur
 101                 e.ca = 0x3
 102                 # create output value
 103                 if value == 0x7ffffffff:
 104                     e.intregs[6] = 0x7fffffffe
 105                 else:
 106                     e.intregs[6] = 0xffff7ffff
 107                 # CR version needs an expected CR
 108                 if '.' in choice:
 109                     e.crregs[0] = 0x4
 110                 self.add_case(Program(lst, bigendian),
 111                               initial_regs, initial_sprs,
 112                               expected=e)
 113
 114     def case_addme_ca_1(self):
 115         insns = ["addme", "addme.", "addmeo", "addmeo."]
 116         for choice in insns:
 117             lst = [f"{choice} 6, 16"]
 118             for value in [0x7ffffffff, # fails, bug #476
 119                           0xffff80000]:
 120                 initial_regs = [0] * 32
 121                 initial_regs[16] = value
 122                 initial_sprs = {}
 123                 xer = SelectableInt(0, 64)
 124                 xer[XER_bits['CA']] = 1 # input carry is 1 (differs from above)
 125                 initial_sprs[special_sprs['XER']] = xer
 126                 e = ExpectedState(pc=4)
 127                 e.intregs[16] = value
 128                 e.ca = 0x3
 129                 if value == 0x7ffffffff:
 130                     e.intregs[6] = 0x7ffffffff
 131                 else:
 132                     e.intregs[6] = 0xffff80000
 133                 if '.' in choice:
 134                     e.crregs[0] = 0x4
 135                 self.add_case(Program(lst, bigendian),
 136                               initial_regs, initial_sprs, expected=e)
 137
 138     def case_addme_ca_so_4(self):
 139         """test of SO being set
 140         """
 141         lst = ["addmeo. 6, 16"]
 142         initial_regs = [0] * 32
 143         initial_regs[16] = 0x7fffffffffffffff
 144         initial_sprs = {}
 145         xer = SelectableInt(0, 64)
 146         xer[XER_bits['CA']] = 1
 147         initial_sprs[special_sprs['XER']] = xer
 148         self.add_case(Program(lst, bigendian),
 149                       initial_regs, initial_sprs)
 150
 151     def case_addme_ca_so_3(self):
 152         """bug where SO does not get passed through to CR0
 153         """
 154         lst = ["addme. 6, 16"]
 155         initial_regs = [0] * 32
 156         initial_regs[16] = 0x7ffffffff
 157         initial_sprs = {}
 158         xer = SelectableInt(0, 64)
 159         xer[XER_bits['CA']] = 1
 160         xer[XER_bits['SO']] = 1
 161         initial_sprs[special_sprs['XER']] = xer
 162         self.add_case(Program(lst, bigendian),
 163                       initial_regs, initial_sprs)
 164
 165     def case_addze(self):
 166         insns = ["addze", "addze.", "addzeo", "addzeo."]
 167         for choice in insns:
 168             lst = [f"{choice} 6, 16"]
 169             initial_regs = [0] * 32
 170             initial_regs[16] = 0x00ff00ff00ff0080
 171             e = ExpectedState(pc=4)
 172             e.intregs[16] = 0xff00ff00ff0080
 173             e.intregs[6] = 0xff00ff00ff0080
 174             if '.' in choice:
 175                 e.crregs[0] = 0x4
 176             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 177
 178     def case_addis_nonzero_r0_regression(self):
 179         lst = [f"addis 3, 0, 1"]
 180         print(lst)
 181         initial_regs = [0] * 32
 182         initial_regs[0] = 5
 183         e = ExpectedState(initial_regs, pc=4)
 184         e.intregs[3] = 0x10000
 185         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 186
 187     def case_addis_nonzero_r0(self):
 188         for i in range(10):
 189             imm = random.randint(-(1 << 15), (1 << 15)-1)
 190             lst = [f"addis 3, 0, {imm}"]
 191             print(lst)
 192             initial_regs = [0] * 32
 193             initial_regs[0] = random.randint(0, (1 << 64)-1)
 194             self.add_case(Program(lst, bigendian), initial_regs)
 195
 196     def case_rand_imm(self):
 197         insns = ["addi", "addis", "subfic"]
 198         for i in range(10):
 199             choice = random.choice(insns)
 200             imm = random.randint(-(1 << 15), (1 << 15)-1)
 201             lst = [f"{choice} 3, 1, {imm}"]
 202             print(lst)
 203             initial_regs = [0] * 32
 204             initial_regs[1] = random.randint(0, (1 << 64)-1)
 205             self.add_case(Program(lst, bigendian), initial_regs)
 206
 207     def case_0_adde(self):
 208         lst = ["adde. 5, 6, 7"]
 209         for i in range(10):
 210             initial_regs = [0] * 32
 211             initial_regs[6] = random.randint(0, (1 << 64)-1)
 212             initial_regs[7] = random.randint(0, (1 << 64)-1)
 213             initial_sprs = {}
 214             xer = SelectableInt(0, 64)
 215             xer[XER_bits['CA']] = 1
 216             initial_sprs[special_sprs['XER']] = xer
 217             self.add_case(Program(lst, bigendian),
 218                           initial_regs, initial_sprs)
 219
 220     def case_cmp(self):
 221         lst = ["subf. 1, 6, 7",
 222                "cmp cr2, 1, 6, 7"]
 223         initial_regs = [0] * 32
 224         initial_regs[6] = 0x10
 225         initial_regs[7] = 0x05
 226         e = ExpectedState(pc=8)
 227         e.intregs[6] = 0x10
 228         e.intregs[7] = 0x5
 229         e.intregs[1] = 0xfffffffffffffff5
 230         e.crregs[0] = 0x8
 231         e.crregs[2] = 0x4
 232         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 233
 234     def case_cmp2(self):
 235         lst = ["cmp cr2, 0, 2, 3"]
 236         initial_regs = [0] * 32
 237         initial_regs[2] = 0xffffffffaaaaaaaa
 238         initial_regs[3] = 0x00000000aaaaaaaa
 239         e = ExpectedState(pc=4)
 240         e.intregs[2] = 0xffffffffaaaaaaaa
 241         e.intregs[3] = 0xaaaaaaaa
 242         e.crregs[2] = 0x2
 243         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 244
 245         lst = ["cmp cr2, 0, 4, 5"]
 246         initial_regs = [0] * 32
 247         initial_regs[4] = 0x00000000aaaaaaaa
 248         initial_regs[5] = 0xffffffffaaaaaaaa
 249         e = ExpectedState(pc=4)
 250         e.intregs[4] = 0xaaaaaaaa
 251         e.intregs[5] = 0xffffffffaaaaaaaa
 252         e.crregs[2] = 0x2
 253         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 254
 255     def case_cmp3(self):
 256         lst = ["cmp cr2, 1, 2, 3"]
 257         initial_regs = [0] * 32
 258         initial_regs[2] = 0xffffffffaaaaaaaa
 259         initial_regs[3] = 0x00000000aaaaaaaa
 260         e = ExpectedState(pc=4)
 261         e.intregs[2] = 0xffffffffaaaaaaaa
 262         e.intregs[3] = 0xaaaaaaaa
 263         e.crregs[2] = 0x8
 264         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 265
 266         lst = ["cmp cr2, 1, 4, 5"]
 267         initial_regs = [0] * 32
 268         initial_regs[4] = 0x00000000aaaaaaaa
 269         initial_regs[5] = 0xffffffffaaaaaaaa
 270         e = ExpectedState(pc=4)
 271         e.intregs[4] = 0xaaaaaaaa
 272         e.intregs[5] = 0xffffffffaaaaaaaa
 273         e.crregs[2] = 0x4
 274         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 275
 276     def case_cmpl_microwatt_0(self):
 277         """microwatt 1.bin:
 278            115b8:   40 50 d1 7c     .long 0x7cd15040 # cmpl 6, 0, 17, 10
 279             register_file.vhdl: Reading GPR 11 000000000001C026
 280             register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
 281             cr_file.vhdl: Reading CR 35055050
 282             cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
 283         """
 284
 285         lst = ["cmpl 6, 0, 17, 10"]
 286         initial_regs = [0] * 32
 287         initial_regs[0x11] = 0x1c026
 288         initial_regs[0xa] =  0xFEDF3FFF0001C025
 289         XER = 0xe00c0000
 290         CR = 0x35055050
 291
 292         self.add_case(Program(lst, bigendian), initial_regs,
 293                                 initial_sprs = {'XER': XER},
 294                                 initial_cr = CR)
 295
 296     def case_cmpl_microwatt_0_disasm(self):
 297         """microwatt 1.bin: disassembled version
 298            115b8:   40 50 d1 7c     .long 0x7cd15040 # cmpl 6, 0, 17, 10
 299             register_file.vhdl: Reading GPR 11 000000000001C026
 300             register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
 301             cr_file.vhdl: Reading CR 35055050
 302             cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
 303         """
 304
 305         dis = ["cmpl 6, 0, 17, 10"]
 306         lst = bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
 307         initial_regs = [0] * 32
 308         initial_regs[0x11] = 0x1c026
 309         initial_regs[0xa] =  0xFEDF3FFF0001C025
 310         XER = 0xe00c0000
 311         CR = 0x35055050
 312
 313         p = Program(lst, bigendian)
 314         p.assembly = '\n'.join(dis)+'\n'
 315         self.add_case(p, initial_regs,
 316                                 initial_sprs = {'XER': XER},
 317                                 initial_cr = CR)
 318
 319     def case_cmplw_microwatt_1(self):
 320         """microwatt 1.bin:
 321            10d94:   40 20 96 7c     cmplw   cr1,r22,r4
 322             gpr: 00000000ffff6dc1 <- r4
 323             gpr: 0000000000000000 <- r22
 324         """
 325
 326         lst = ["cmpl 1, 0, 22, 4"]
 327         initial_regs = [0] * 32
 328         initial_regs[4] = 0xffff6dc1
 329         initial_regs[22] = 0
 330         XER = 0xe00c0000
 331         CR = 0x50759999
 332
 333         self.add_case(Program(lst, bigendian), initial_regs,
 334                                 initial_sprs = {'XER': XER},
 335                                 initial_cr = CR)
 336
 337     def case_cmpli_microwatt(self):
 338         """microwatt 1.bin: cmpli
 339            123ac:   9c 79 8d 2a     cmpli   cr5,0,r13,31132
 340             gpr: 00000000301fc7a7 <- r13
 341             cr : 0000000090215393
 342             xer: so 1 ca 0 32 0 ov 0 32 0
 343
 344         """
 345
 346         lst = ["cmpli 5, 0, 13, 31132"]
 347         initial_regs = [0] * 32
 348         initial_regs[13] = 0x301fc7a7
 349         XER = 0xe00c0000
 350         CR = 0x90215393
 351
 352         self.add_case(Program(lst, bigendian), initial_regs,
 353                                 initial_sprs = {'XER': XER},
 354                                 initial_cr = CR)
 355
 356     def case_extsb(self):
 357         insns = ["extsb", "extsh", "extsw"]
 358         for i in range(10):
 359             choice = random.choice(insns)
 360             lst = [f"{choice} 3, 1"]
 361             print(lst)
 362             initial_regs = [0] * 32
 363             initial_regs[1] = random.randint(0, (1 << 64)-1)
 364             self.add_case(Program(lst, bigendian), initial_regs)
 365
 366     def case_cmpeqb(self):
 367         lst = ["cmpeqb cr1, 1, 2"]
 368         for i in range(20):
 369             initial_regs = [0] * 32
 370             initial_regs[1] = i
 371             initial_regs[2] = 0x0001030507090b0f
 372             self.add_case(Program(lst, bigendian), initial_regs, {})
 373