src/openpower/test/alu/alu_cases.py

   1 import random
   2 from openpower.test.common import TestAccumulatorBase
   3 from openpower.endian import bigendian
   4 from openpower.simulator.program import Program
   5 from openpower.decoder.selectable_int import SelectableInt
   6 from openpower.decoder.power_enums import XER_bits
   7 from openpower.decoder.isa.caller import special_sprs
   8 from openpower.test.state import ExpectedState
   9 import unittest
  10
  11
  12 class ALUTestCase(TestAccumulatorBase):
  13
  14     def case_1_regression(self):
  15         lst = [f"add. 3, 1, 2"]
  16         initial_regs = [0] * 32
  17         initial_regs[1] = 0xc523e996a8ff6215
  18         initial_regs[2] = 0xe1e5b9cc9864c4a8
  19         e = ExpectedState(pc=4)
  20         e.intregs[1] = 0xc523e996a8ff6215
  21         e.intregs[2] = 0xe1e5b9cc9864c4a8
  22         e.intregs[3] = 0xa709a363416426bd
  23         e.crregs[0] = 0x8
  24         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  25
  26     def case_2_regression(self):
  27         lst = [f"extsw 3, 1"]
  28         initial_regs = [0] * 32
  29         initial_regs[1] = 0xb6a1fc6c8576af91
  30         e = ExpectedState(pc=4)
  31         e.intregs[1] = 0xb6a1fc6c8576af91
  32         e.intregs[3] = 0xffffffff8576af91
  33         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  34
  35         lst = [f"subf 3, 1, 2"]
  36         initial_regs = [0] * 32
  37         initial_regs[1] = 0x3d7f3f7ca24bac7b
  38         initial_regs[2] = 0xf6b2ac5e13ee15c2
  39         e = ExpectedState(pc=4)
  40         e.intregs[1] = 0x3d7f3f7ca24bac7b
  41         e.intregs[2] = 0xf6b2ac5e13ee15c2
  42         e.intregs[3] = 0xb9336ce171a26947
  43         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  44
  45         lst = [f"subf 3, 1, 2"]
  46         initial_regs = [0] * 32
  47         initial_regs[1] = 0x833652d96c7c0058
  48         initial_regs[2] = 0x1c27ecff8a086c1a
  49         e = ExpectedState(pc=4)
  50         e.intregs[1] = 0x833652d96c7c0058
  51         e.intregs[2] = 0x1c27ecff8a086c1a
  52         e.intregs[3] = 0x98f19a261d8c6bc2
  53         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  54
  55         lst = [f"extsb 3, 1"]
  56         initial_regs = [0] * 32
  57         initial_regs[1] = 0x7f9497aaff900ea0
  58         e = ExpectedState(pc=4)
  59         e.intregs[1] = 0x7f9497aaff900ea0
  60         e.intregs[3] = 0xffffffffffffffa0
  61         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  62
  63         lst = [f"add 3, 1, 2"]
  64         initial_regs = [0] * 32
  65         initial_regs[1] = 0x2e08ae202742baf8
  66         initial_regs[2] = 0x86c43ece9efe5baa
  67         e = ExpectedState(pc=4)
  68         e.intregs[1] = 0x2e08ae202742baf8
  69         e.intregs[2] = 0x86c43ece9efe5baa
  70         e.intregs[3] = 0xb4cceceec64116a2
  71         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  72
  73     def case_rand(self):
  74         insns = ["add", "add.", "subf"]
  75         for i in range(40):
  76             choice = random.choice(insns)
  77             lst = [f"{choice} 3, 1, 2"]
  78             initial_regs = [0] * 32
  79             initial_regs[1] = random.randint(0, (1 << 64)-1)
  80             initial_regs[2] = random.randint(0, (1 << 64)-1)
  81             self.add_case(Program(lst, bigendian), initial_regs)
  82
  83     def case_addme_ca_0(self):
  84         insns = ["addme", "addme.", "addmeo", "addmeo."]
  85         for choice in insns:
  86             lst = [f"{choice} 6, 16"]
  87             for value in [0x7ffffffff,
  88                           0xffff80000]:
  89                 initial_regs = [0] * 32
  90                 initial_regs[16] = value
  91                 initial_sprs = {}
  92                 xer = SelectableInt(0, 64)
  93                 xer[XER_bits['CA']] = 0  # input carry is 0 (see test below)
  94                 initial_sprs[special_sprs['XER']] = xer
  95
  96                 # create expected results.  pc should be 4 (one instruction)
  97                 e = ExpectedState(pc=4)
  98                 # input value should not be modified
  99                 e.intregs[16] = value
 100                 # carry-out should always occur
 101                 e.ca = 0x3
 102                 # create output value
 103                 if value == 0x7ffffffff:
 104                     e.intregs[6] = 0x7fffffffe
 105                 else:
 106                     e.intregs[6] = 0xffff7ffff
 107                 # CR version needs an expected CR
 108                 if '.' in choice:
 109                     e.crregs[0] = 0x4
 110                 self.add_case(Program(lst, bigendian),
 111                               initial_regs, initial_sprs,
 112                               expected=e)
 113
 114     def case_addme_ca_1(self):
 115         insns = ["addme", "addme.", "addmeo", "addmeo."]
 116         for choice in insns:
 117             lst = [f"{choice} 6, 16"]
 118             for value in [0x7ffffffff, # fails, bug #476
 119                           0xffff80000]:
 120                 initial_regs = [0] * 32
 121                 initial_regs[16] = value
 122                 initial_sprs = {}
 123                 xer = SelectableInt(0, 64)
 124                 xer[XER_bits['CA']] = 1 # input carry is 1 (differs from above)
 125                 initial_sprs[special_sprs['XER']] = xer
 126                 e = ExpectedState(pc=4)
 127                 e.intregs[16] = value
 128                 e.ca = 0x3
 129                 if value == 0x7ffffffff:
 130                     e.intregs[6] = 0x7ffffffff
 131                 else:
 132                     e.intregs[6] = 0xffff80000
 133                 if '.' in choice:
 134                     e.crregs[0] = 0x4
 135                 self.add_case(Program(lst, bigendian),
 136                               initial_regs, initial_sprs, expected=e)
 137
 138     def case_addme_ca_so_4(self):
 139         """test of SO being set
 140         """
 141         lst = ["addmeo. 6, 16"]
 142         initial_regs = [0] * 32
 143         initial_regs[16] = 0x7fffffffffffffff
 144         initial_sprs = {}
 145         xer = SelectableInt(0, 64)
 146         xer[XER_bits['CA']] = 1
 147         initial_sprs[special_sprs['XER']] = xer
 148         e = ExpectedState(pc=4)
 149         e.intregs[16] = 0x7fffffffffffffff
 150         e.intregs[6] = 0x7fffffffffffffff
 151         e.ca = 0x3
 152         e.crregs[0] = 0x4
 153         self.add_case(Program(lst, bigendian),
 154                       initial_regs, initial_sprs, expected=e)
 155
 156     def case_addme_ca_so_3(self):
 157         """bug where SO does not get passed through to CR0
 158         """
 159         lst = ["addme. 6, 16"]
 160         initial_regs = [0] * 32
 161         initial_regs[16] = 0x7ffffffff
 162         initial_sprs = {}
 163         xer = SelectableInt(0, 64)
 164         xer[XER_bits['CA']] = 1
 165         xer[XER_bits['SO']] = 1
 166         initial_sprs[special_sprs['XER']] = xer
 167         e = ExpectedState(pc=4)
 168         e.intregs[16] = 0x7ffffffff
 169         e.intregs[6] = 0x7ffffffff
 170         e.crregs[0] = 0x5
 171         e.so = 0x1
 172         e.ca = 0x3
 173         self.add_case(Program(lst, bigendian),
 174                       initial_regs, initial_sprs, expected=e)
 175
 176     def case_addze(self):
 177         insns = ["addze", "addze.", "addzeo", "addzeo."]
 178         for choice in insns:
 179             lst = [f"{choice} 6, 16"]
 180             initial_regs = [0] * 32
 181             initial_regs[16] = 0x00ff00ff00ff0080
 182             e = ExpectedState(pc=4)
 183             e.intregs[16] = 0xff00ff00ff0080
 184             e.intregs[6] = 0xff00ff00ff0080
 185             if '.' in choice:
 186                 e.crregs[0] = 0x4
 187             self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 188
 189     def case_addis_nonzero_r0_regression(self):
 190         lst = [f"addis 3, 0, 1"]
 191         print(lst)
 192         initial_regs = [0] * 32
 193         initial_regs[0] = 5
 194         e = ExpectedState(initial_regs, pc=4)
 195         e.intregs[3] = 0x10000
 196         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 197
 198     def case_addis_nonzero_r0(self):
 199         for i in range(10):
 200             imm = random.randint(-(1 << 15), (1 << 15)-1)
 201             lst = [f"addis 3, 0, {imm}"]
 202             print(lst)
 203             initial_regs = [0] * 32
 204             initial_regs[0] = random.randint(0, (1 << 64)-1)
 205             self.add_case(Program(lst, bigendian), initial_regs)
 206
 207     def case_rand_imm(self):
 208         insns = ["addi", "addis", "subfic"]
 209         for i in range(10):
 210             choice = random.choice(insns)
 211             imm = random.randint(-(1 << 15), (1 << 15)-1)
 212             lst = [f"{choice} 3, 1, {imm}"]
 213             print(lst)
 214             initial_regs = [0] * 32
 215             initial_regs[1] = random.randint(0, (1 << 64)-1)
 216             self.add_case(Program(lst, bigendian), initial_regs)
 217
 218     def case_0_adde(self):
 219         lst = ["adde. 5, 6, 7"]
 220         for i in range(10):
 221             initial_regs = [0] * 32
 222             initial_regs[6] = random.randint(0, (1 << 64)-1)
 223             initial_regs[7] = random.randint(0, (1 << 64)-1)
 224             initial_sprs = {}
 225             xer = SelectableInt(0, 64)
 226             xer[XER_bits['CA']] = 1
 227             initial_sprs[special_sprs['XER']] = xer
 228             self.add_case(Program(lst, bigendian),
 229                           initial_regs, initial_sprs)
 230
 231     def case_cmp(self):
 232         lst = ["subf. 1, 6, 7",
 233                "cmp cr2, 1, 6, 7"]
 234         initial_regs = [0] * 32
 235         initial_regs[6] = 0x10
 236         initial_regs[7] = 0x05
 237         e = ExpectedState(pc=8)
 238         e.intregs[6] = 0x10
 239         e.intregs[7] = 0x5
 240         e.intregs[1] = 0xfffffffffffffff5
 241         e.crregs[0] = 0x8
 242         e.crregs[2] = 0x4
 243         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 244
 245     def case_cmp2(self):
 246         lst = ["cmp cr2, 0, 2, 3"]
 247         initial_regs = [0] * 32
 248         initial_regs[2] = 0xffffffffaaaaaaaa
 249         initial_regs[3] = 0x00000000aaaaaaaa
 250         e = ExpectedState(pc=4)
 251         e.intregs[2] = 0xffffffffaaaaaaaa
 252         e.intregs[3] = 0xaaaaaaaa
 253         e.crregs[2] = 0x2
 254         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 255
 256         lst = ["cmp cr2, 0, 4, 5"]
 257         initial_regs = [0] * 32
 258         initial_regs[4] = 0x00000000aaaaaaaa
 259         initial_regs[5] = 0xffffffffaaaaaaaa
 260         e = ExpectedState(pc=4)
 261         e.intregs[4] = 0xaaaaaaaa
 262         e.intregs[5] = 0xffffffffaaaaaaaa
 263         e.crregs[2] = 0x2
 264         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 265
 266     def case_cmp3(self):
 267         lst = ["cmp cr2, 1, 2, 3"]
 268         initial_regs = [0] * 32
 269         initial_regs[2] = 0xffffffffaaaaaaaa
 270         initial_regs[3] = 0x00000000aaaaaaaa
 271         e = ExpectedState(pc=4)
 272         e.intregs[2] = 0xffffffffaaaaaaaa
 273         e.intregs[3] = 0xaaaaaaaa
 274         e.crregs[2] = 0x8
 275         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 276
 277         lst = ["cmp cr2, 1, 4, 5"]
 278         initial_regs = [0] * 32
 279         initial_regs[4] = 0x00000000aaaaaaaa
 280         initial_regs[5] = 0xffffffffaaaaaaaa
 281         e = ExpectedState(pc=4)
 282         e.intregs[4] = 0xaaaaaaaa
 283         e.intregs[5] = 0xffffffffaaaaaaaa
 284         e.crregs[2] = 0x4
 285         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 286
 287     def case_cmpl_microwatt_0(self):
 288         """microwatt 1.bin:
 289            115b8:   40 50 d1 7c     .long 0x7cd15040 # cmpl 6, 0, 17, 10
 290             register_file.vhdl: Reading GPR 11 000000000001C026
 291             register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
 292             cr_file.vhdl: Reading CR 35055050
 293             cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
 294         """
 295
 296         lst = ["cmpl 6, 0, 17, 10"]
 297         initial_regs = [0] * 32
 298         initial_regs[0x11] = 0x1c026
 299         initial_regs[0xa] =  0xFEDF3FFF0001C025
 300         XER = 0xe00c0000
 301         CR = 0x35055050
 302
 303         e = ExpectedState(pc=4)
 304         e.intregs[10] = 0xfedf3fff0001c025
 305         e.intregs[17] = 0x1c026
 306         e.crregs[0] = 0x3
 307         e.crregs[1] = 0x5
 308         e.crregs[3] = 0x5
 309         e.crregs[4] = 0x5
 310         e.crregs[6] = 0x5
 311         e.so = 0x1
 312         e.ov = 0x3
 313         e.ca = 0x3
 314
 315         self.add_case(Program(lst, bigendian), initial_regs,
 316                                 initial_sprs = {'XER': XER},
 317                                 initial_cr = CR, expected=e)
 318
 319     def case_cmpl_microwatt_0_disasm(self):
 320         """microwatt 1.bin: disassembled version
 321            115b8:   40 50 d1 7c     .long 0x7cd15040 # cmpl 6, 0, 17, 10
 322             register_file.vhdl: Reading GPR 11 000000000001C026
 323             register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
 324             cr_file.vhdl: Reading CR 35055050
 325             cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
 326         """
 327
 328         dis = ["cmpl 6, 0, 17, 10"]
 329         lst = bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
 330         initial_regs = [0] * 32
 331         initial_regs[0x11] = 0x1c026
 332         initial_regs[0xa] =  0xFEDF3FFF0001C025
 333         XER = 0xe00c0000
 334         CR = 0x35055050
 335
 336         p = Program(lst, bigendian)
 337         p.assembly = '\n'.join(dis)+'\n'
 338         self.add_case(p, initial_regs,
 339                                 initial_sprs = {'XER': XER},
 340                                 initial_cr = CR)
 341
 342     def case_cmplw_microwatt_1(self):
 343         """microwatt 1.bin:
 344            10d94:   40 20 96 7c     cmplw   cr1,r22,r4
 345             gpr: 00000000ffff6dc1 <- r4
 346             gpr: 0000000000000000 <- r22
 347         """
 348
 349         lst = ["cmpl 1, 0, 22, 4"]
 350         initial_regs = [0] * 32
 351         initial_regs[4] = 0xffff6dc1
 352         initial_regs[22] = 0
 353         XER = 0xe00c0000
 354         CR = 0x50759999
 355
 356         self.add_case(Program(lst, bigendian), initial_regs,
 357                                 initial_sprs = {'XER': XER},
 358                                 initial_cr = CR)
 359
 360     def case_cmpli_microwatt(self):
 361         """microwatt 1.bin: cmpli
 362            123ac:   9c 79 8d 2a     cmpli   cr5,0,r13,31132
 363             gpr: 00000000301fc7a7 <- r13
 364             cr : 0000000090215393
 365             xer: so 1 ca 0 32 0 ov 0 32 0
 366
 367         """
 368
 369         lst = ["cmpli 5, 0, 13, 31132"]
 370         initial_regs = [0] * 32
 371         initial_regs[13] = 0x301fc7a7
 372         XER = 0xe00c0000
 373         CR = 0x90215393
 374
 375         self.add_case(Program(lst, bigendian), initial_regs,
 376                                 initial_sprs = {'XER': XER},
 377                                 initial_cr = CR)
 378
 379     def case_extsb(self):
 380         insns = ["extsb", "extsh", "extsw"]
 381         for i in range(10):
 382             choice = random.choice(insns)
 383             lst = [f"{choice} 3, 1"]
 384             print(lst)
 385             initial_regs = [0] * 32
 386             initial_regs[1] = random.randint(0, (1 << 64)-1)
 387             self.add_case(Program(lst, bigendian), initial_regs)
 388
 389     def case_cmpeqb(self):
 390         lst = ["cmpeqb cr1, 1, 2"]
 391         for i in range(20):
 392             initial_regs = [0] * 32
 393             initial_regs[1] = i
 394             initial_regs[2] = 0x0001030507090b0f
 395             self.add_case(Program(lst, bigendian), initial_regs, {})
 396