fix fmvis decoder, it's now a 2-operand instruction
[openpower-isa.git] / src / openpower / test / alu / fmvis_cases.py
1 from openpower.sv.trans.svp64 import SVP64Asm
2 import random
3 from openpower.test.common import TestAccumulatorBase
4 from openpower.endian import bigendian
5 from openpower.simulator.program import Program
6 from openpower.decoder.selectable_int import SelectableInt
7 from openpower.decoder.power_enums import XER_bits
8 from openpower.decoder.isa.caller import special_sprs
9 from openpower.decoder.helpers import exts
10 from openpower.test.state import ExpectedState
11 import unittest
12
13 class FMVISTestCase(TestAccumulatorBase):
14
15 def case_0_fmvis(self):
16 lst = SVP64Asm(["fmvis 5, 0x4000",
17 "fmvis 6, 0x2122",
18 "fmvis 7, 0x3E80",
19 ])
20 lst = list(lst)
21
22 expected_fprs = [0] * 32
23 expected_fprs[5] = 0x40000000
24 expected_fprs[6] = 0x21220000
25 expected_fprs[7] = 0x3E800000
26 self.add_case(Program(lst, bigendian), expected_fprs)