src/openpower/test/alu/maddsubrs_cases.py

   1 from openpower.sv.trans.svp64 import SVP64Asm
   2 import random
   3 from openpower.test.common import TestAccumulatorBase, skip_case
   4 from openpower.endian import bigendian
   5 from openpower.simulator.program import Program
   6 from openpower.decoder.selectable_int import SelectableInt
   7 from openpower.decoder.power_enums import XER_bits
   8 from openpower.decoder.isa.caller import SVP64State
   9 from openpower.decoder.helpers import exts
  10 from openpower.test.state import ExpectedState
  11 import unittest
  12 import math
  13
  14 class MADDSUBRSTestCase(TestAccumulatorBase):
  15
  16     def case_0_maddsubrs(self):
  17         isa = SVP64Asm(["maddsubrs 1,10,14,11"])
  18         lst = list(isa)
  19
  20         initial_regs = [0] * 32
  21         initial_regs[1] = 0x00000a71
  22         initial_regs[10] = 0x0000e6b8
  23         initial_regs[11] = 0x00002d41
  24
  25         e = ExpectedState(pc=4)
  26         e.intregs[1] = 0x0000aa86
  27         e.intregs[2] = 0xffffffffffff643e
  28         e.intregs[10] = 0x0000e6b8
  29         e.intregs[11] = 0x00002d41
  30         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  31
  32     def case_1_maddsubrs(self):
  33         isa = SVP64Asm(["maddsubrs 1,10,0,11"])
  34         lst = list(isa)
  35
  36         initial_regs = [0] * 32
  37         initial_regs[1] = 0x00000a71
  38         initial_regs[10] = 0x0000e6b8
  39         initial_regs[11] = 0x00002d41
  40
  41         e = ExpectedState(pc=4)
  42         e.intregs[1] = 0x2aa17069
  43         e.intregs[2] = 0xffffffffd90f96f9
  44         e.intregs[10] = 0x0000e6b8
  45         e.intregs[11] = 0x00002d41
  46         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  47
  48     def case_2_maddsubrs(self):
  49         isa = SVP64Asm(["maddsubrs 1,10,2,11"])
  50         lst = list(isa)
  51
  52         initial_regs = [0] * 32
  53         initial_regs[1] = 0x100000000
  54         initial_regs[10] = 0x000000003
  55         initial_regs[11] = 0x10000000
  56
  57         e = ExpectedState(pc=4)
  58         e.intregs[1] = 0x40000000c000000;
  59         e.intregs[2] = 0x3fffffff4000000;
  60         e.intregs[10] = 0x00000003
  61         e.intregs[11] = 0x10000000;
  62         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  63
  64     def case_3_maddsubrs(self):
  65         isa = SVP64Asm(["maddsubrs 1,10,16,11"])
  66         lst = list(isa)
  67
  68         initial_regs = [0] * 32
  69         initial_regs[1] = 0x100000000
  70         initial_regs[10] = 0x000000003
  71         initial_regs[11] = 0x10000000
  72
  73         e = ExpectedState(pc=4)
  74         e.intregs[1] = 0x100000003000;
  75         e.intregs[2] = 0x0fffffffd000;
  76         e.intregs[10] = 0x00000003
  77         e.intregs[11] = 0x10000000;
  78         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  79
  80     def case_4_maddsubrs(self):
  81         isa = SVP64Asm(["maddsubrs 1,10,1,11"])
  82         lst = list(isa)
  83
  84         initial_regs = [0] * 32
  85         initial_regs[1] = 0x100000000
  86         initial_regs[10] = 0x000000003
  87         initial_regs[11] = 0xff0000000
  88
  89         e = ExpectedState(pc=4)
  90         e.intregs[1] = 0xf8000017e8000000;
  91         e.intregs[2] = 0xf7ffffe818000000;
  92         e.intregs[10] = 0x000000003
  93         e.intregs[11] = 0xff0000000;
  94         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  95
  96     def case_maddsubrs_16bit_s14(self):
  97         p = Program(list(SVP64Asm([
  98             "sv.maddsubrs/w=16 *10,*20,14,*30",
  99         ])), bigendian)
 100
 101         initial_regs = [0] * 32
 102
 103         # use somewhat reasonable i16 values since we're working in
 104         # 2.14-bit fixed-point
 105
 106         initial_regs[10] = 0x1000_2000_3000_4000  # 0x0.4, 0x0.8, 0x0.c, 0x1.0
 107
 108         # 0x0.48d0, -0x0.0490, 0x0.d158, -0x0.48d4
 109         initial_regs[20] = 0x1234_fedc_3456_edcb
 110         cospi_16_64 = 11585  # from libvpx -- 0x0.b504 ~ 0.70709 ~ cos(pi/4)
 111         initial_regs[30] = cospi_16_64 * 0x1_0001_0001_0001  # splat 4x
 112
 113         svstate = SVP64State()
 114         svstate.vl = 4
 115         svstate.maxvl = 4
 116
 117         e = ExpectedState(pc=8, int_regs=initial_regs)
 118         e.intregs[10] = 0
 119         e.intregs[11] = 0
 120         for i in range(svstate.vl):
 121             rt = (initial_regs[10] >> (i * 16)) & 0xFFFF  # extract element
 122             rt -= (rt & 0x8000) << 1  # sign extend rt
 123             ra = (initial_regs[20] >> (i * 16)) & 0xFFFF
 124             ra -= (ra & 0x8000) << 1  # sign extend ra
 125             rb = (initial_regs[30] >> (i * 16)) & 0xFFFF
 126             rb -= (rb & 0x8000) << 1  # sign extend rb
 127             s = rt + ra
 128             d = rt - ra
 129             # f64 is big enough to represent all relevant values exactly,
 130             # so we can use float
 131             rt = math.floor((s * rb) / (2 ** 14) + 0.5)  # mul & round & shr
 132             rs = math.floor((d * rb) / (2 ** 14) + 0.5)
 133             e.intregs[10] |= (rt & 0xFFFF) << (16 * i)  # insert element
 134             e.intregs[11] |= (rs & 0xFFFF) << (16 * i)
 135
 136         # asserts so you can read the expected values
 137         assert e.intregs[10] == 0x182f_15d2_46f2_2061
 138         assert e.intregs[11] == 0xfe71_176f_fcef_3a21
 139
 140         self.add_case(p, initial_regs, expected=e, initial_svstate=svstate)
 141
 142     def case_0_maddrs(self):
 143         isa = SVP64Asm(["maddsubrs 1,10,0,11",
 144                         "maddrs 1,10,0,12"])
 145         lst = list(isa)
 146
 147         initial_regs = [0] * 32
 148         initial_regs[1] = 0x00000a71
 149         initial_regs[10] = 0x0000e6b8
 150         initial_regs[11] = 0x00002d41
 151         initial_regs[12] = 0x00000d00
 152
 153         e = ExpectedState(pc=8)
 154         e.intregs[1] = 0x3658c869
 155         e.intregs[2] = 0xffffffffcd583ef9
 156         e.intregs[10] = 0x0000e6b8
 157         e.intregs[11] = 0x00002d41
 158         e.intregs[12] = 0x00000d00
 159         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 160
 161     def case_1_maddrs(self):
 162         isa = SVP64Asm(["maddsubrs 1,10,0,11",
 163                         "maddrs 1,10,14,12"])
 164         lst = list(isa)
 165
 166         initial_regs = [0] * 32
 167         initial_regs[1] = 0x00000a71
 168         initial_regs[10] = 0x0000e6b8
 169         initial_regs[11] = 0x00002d41
 170         initial_regs[12] = 0x00000d00
 171
 172         e = ExpectedState(pc=8)
 173         e.intregs[1] = 0x0000d963
 174         e.intregs[2] = 0xffffffffffff3561
 175         e.intregs[10] = 0x0000e6b8
 176         e.intregs[11] = 0x00002d41
 177         e.intregs[12] = 0x00000d00
 178         self.add_case(Program(lst, bigendian), initial_regs, expected=e)