src/openpower/test/bigint/shadd_cases.py

   1 from openpower.test.common import TestAccumulatorBase, skip_case
   2 from openpower.insndb.asm import SVP64Asm
   3 from openpower.test.state import ExpectedState
   4 from openpower.simulator.program import Program
   5 from openpower.decoder.isa.caller import SVP64State
   6 from openpower.decoder.helpers import exts
   7
   8
   9 _MASK32 = ((2 ** 32) - 1)
  10 _MASK64 = ((2 ** 64) - 1)
  11
  12
  13 class ShiftAddCases(TestAccumulatorBase):
  14
  15     def case_sadd(self):
  16         for SH in range(4):
  17             with self.subTest(SH=SH):
  18                 insn = ("sadd 3,4,5,%d" % SH)
  19                 prog = Program(list(SVP64Asm([insn])), False)
  20                 gprs = [0] * 32
  21                 gprs[3] = 0x01234567890abcde
  22                 RA = gprs[4] = 0xf00dcafedeadbeef
  23                 RB = gprs[5] = 0xabadbabedefec8ed
  24                 RT = ((((RB << (SH+1)) & _MASK64) + RA) & _MASK64)
  25                 e = ExpectedState(pc=4, int_regs=gprs)
  26                 e.intregs[3] = RT
  27                 self.add_case(prog, gprs, expected=e)
  28
  29     def case_saddw(self):
  30         for SH in range(4):
  31             with self.subTest(SH=SH):
  32                 insn = ("saddw 3,4,5,%d" % SH)
  33                 prog = Program(list(SVP64Asm([insn])), False)
  34                 gprs = [0] * 32
  35                 gprs[3] = 0x01234567890abcde
  36                 RA = gprs[4] = 0xf00dcafedeadbeef
  37                 RB = gprs[5] = 0xabadbabedefec8ed
  38                 RB_i32 = RB & _MASK32
  39                 if RB_i32 >> 31:
  40                     RB_i32 -= 1 << 32
  41                 RT = ((((RB_i32 << (SH+1)) & _MASK64) + RA) & _MASK64)
  42                 e = ExpectedState(pc=4, int_regs=gprs)
  43                 e.intregs[3] = RT
  44                 self.add_case(prog, gprs, expected=e)
  45
  46     def case_sadduw(self):
  47         for SH in range(4):
  48             with self.subTest(SH=SH):
  49                 insn = ("sadduw 3,4,5,%d" % SH)
  50                 prog = Program(list(SVP64Asm([insn])), False)
  51                 gprs = [0] * 32
  52                 gprs[3] = 0x01234567890abcde
  53                 RA = gprs[4] = 0xf00dcafedeadbeef
  54                 RB = gprs[5] = 0xabadbabedefec8ed
  55                 RT = (((((RB & _MASK32) << (SH+1)) & _MASK64) + RA) & _MASK64)
  56                 e = ExpectedState(pc=4, int_regs=gprs)
  57                 e.intregs[3] = RT
  58                 self.add_case(prog, gprs, expected=e)
  59