1 from openpower
.insndb
.asm
import SVP64Asm
3 from openpower
.test
.common
import TestAccumulatorBase
4 from openpower
.endian
import bigendian
5 from openpower
.simulator
.program
import Program
6 from openpower
.decoder
.selectable_int
import SelectableInt
7 from openpower
.decoder
.power_enums
import XER_bits
8 from openpower
.decoder
.isa
.caller
import special_sprs
9 from openpower
.decoder
.helpers
import exts
10 from openpower
.test
.state
import ExpectedState
14 class AVTestCase(TestAccumulatorBase
):
16 def case_0_maxs(self
):
17 lst
= ["minmax 3, 1, 2, 3"]
18 lst
= list(SVP64Asm(lst
, bigendian
))
20 initial_regs
= [0] * 32
21 initial_regs
[1] = 0xc523e996a8ff6215
22 initial_regs
[2] = 0xe1e5b9cc9864c4a8
23 e
= ExpectedState(pc
=4)
24 e
.intregs
[1] = 0xc523e996a8ff6215
25 e
.intregs
[2] = 0xe1e5b9cc9864c4a8
26 e
.intregs
[3] = 0xe1e5b9cc9864c4a8
27 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
29 def case_1_maxs(self
):
30 lst
= ["minmax 3, 1, 2, 3"]
31 lst
= list(SVP64Asm(lst
, bigendian
))
33 initial_regs
= [0] * 32
34 initial_regs
[1] = 0xe1e5b9cc9864c4a8
35 initial_regs
[2] = 0xc523e996a8ff6215
36 e
= ExpectedState(pc
=4)
37 e
.intregs
[1] = 0xe1e5b9cc9864c4a8
38 e
.intregs
[2] = 0xc523e996a8ff6215
39 e
.intregs
[3] = 0xe1e5b9cc9864c4a8
40 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
42 def case_2_maxs_(self
):
43 lst
= [f
"minmax. 3, 1, 2, 3"]
44 lst
= list(SVP64Asm(lst
, bigendian
))
46 initial_regs
= [0] * 32
47 initial_regs
[1] = 0xc523e996a8ff6215
48 initial_regs
[2] = 0xe1e5b9cc9864c4a8
49 e
= ExpectedState(pc
=4)
50 e
.intregs
[1] = 0xc523e996a8ff6215
51 e
.intregs
[2] = 0xe1e5b9cc9864c4a8
52 e
.intregs
[3] = 0xe1e5b9cc9864c4a8
54 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
56 def case_3_maxs_(self
):
57 lst
= [f
"minmax. 3, 1, 2, 3"]
58 lst
= list(SVP64Asm(lst
, bigendian
))
60 initial_regs
= [0] * 32
61 initial_regs
[1] = 0xc523e996a8ff6215
63 e
= ExpectedState(pc
=4)
64 e
.intregs
[1] = 0xc523e996a8ff6215
67 e
.crregs
[0] = 0x8 # RB greater (arithmeticslly)
68 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
70 def case_4_maxs_(self
):
71 lst
= [f
"minmax. 3, 1, 2, 3"]
72 lst
= list(SVP64Asm(lst
, bigendian
))
74 initial_regs
= [0] * 32
77 e
= ExpectedState(pc
=4)
81 e
.crregs
[0] = 0x4 # RT is +ve
82 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
84 def case_5_maxs_(self
):
85 """max negative number compared against +ve number
87 lst
= [f
"minmax. 3, 1, 2, 3"]
88 lst
= list(SVP64Asm(lst
, bigendian
))
90 initial_regs
= [0] * 32
92 initial_regs
[2] = 0x8000_0000_0000_0000
93 e
= ExpectedState(pc
=4)
95 e
.intregs
[2] = 0x8000_0000_0000_0000
97 e
.crregs
[0] = 0x4 # RT is +ve
98 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
100 def case_6_maxs_(self
):
101 lst
= [f
"minmax. 3, 1, 2, 3"]
102 lst
= list(SVP64Asm(lst
, bigendian
))
104 initial_regs
= [0] * 32
105 initial_regs
[1] = 0x8000_0000_0000_0000
106 initial_regs
[2] = 0x8000_0000_0000_0000
107 e
= ExpectedState(pc
=4)
108 e
.intregs
[1] = 0x8000_0000_0000_0000
109 e
.intregs
[2] = 0x8000_0000_0000_0000
110 e
.intregs
[3] = 0x8000_0000_0000_0000
111 e
.crregs
[0] = 0x2 # values are equal
112 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
114 def case_0_mins(self
):
115 lst
= ["minmax 3, 1, 2, 2"]
116 lst
= list(SVP64Asm(lst
, bigendian
))
118 initial_regs
= [0] * 32
119 initial_regs
[1] = 0xc523e996a8ff6215
120 initial_regs
[2] = 0xe1e5b9cc9864c4a8
121 e
= ExpectedState(pc
=4)
122 e
.intregs
[1] = 0xc523e996a8ff6215
123 e
.intregs
[2] = 0xe1e5b9cc9864c4a8
124 e
.intregs
[3] = 0xc523e996a8ff6215
125 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
127 def case_2_mins_(self
):
128 lst
= [f
"minmax. 3, 1, 2, 2"]
129 lst
= list(SVP64Asm(lst
, bigendian
))
131 initial_regs
= [0] * 32
132 initial_regs
[1] = 0xc523e996a8ff6215
133 initial_regs
[2] = 0xe1e5b9cc9864c4a8
134 e
= ExpectedState(pc
=4)
135 e
.intregs
[1] = 0xc523e996a8ff6215
136 e
.intregs
[2] = 0xe1e5b9cc9864c4a8
137 e
.intregs
[3] = 0xc523e996a8ff6215
139 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
141 def case_5_mins_(self
):
142 """min negative number compared against +ve number
144 lst
= [f
"minmax. 3, 1, 2, 2"]
145 lst
= list(SVP64Asm(lst
, bigendian
))
147 initial_regs
= [0] * 32
149 initial_regs
[2] = 0x8000_0000_0000_0000
150 e
= ExpectedState(pc
=4)
152 e
.intregs
[2] = 0x8000_0000_0000_0000
153 e
.intregs
[3] = 0x8000_0000_0000_0000
154 e
.crregs
[0] = 0x4 # r1 >s r2
155 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
157 def case_0_maxu(self
):
158 lst
= ["minmax 3, 1, 2, 1"]
159 lst
= list(SVP64Asm(lst
, bigendian
))
161 initial_regs
= [0] * 32
162 initial_regs
[1] = 0xc523e996a8ff6215
163 initial_regs
[2] = 0xe1e5b9cc9864c4a8
164 e
= ExpectedState(pc
=4)
165 e
.intregs
[1] = 0xc523e996a8ff6215
166 e
.intregs
[2] = 0xe1e5b9cc9864c4a8
167 e
.intregs
[3] = 0xe1e5b9cc9864c4a8
168 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
170 def case_5_minu_(self
):
173 lst
= [f
"minmax. 3, 1, 2, 0"]
174 lst
= list(SVP64Asm(lst
, bigendian
))
176 initial_regs
= [0] * 32
178 initial_regs
[2] = 0x8000_0000_0000_0000
179 e
= ExpectedState(pc
=4)
181 e
.intregs
[2] = 0x8000_0000_0000_0000
182 e
.intregs
[3] = min(e
.intregs
[1], e
.intregs
[2])
183 e
.crregs
[0] = 0x8 # r1 <u r2
184 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
186 def case_0_avgadd(self
):
187 lst
= ["avgadd 3, 1, 2"]
188 lst
= list(SVP64Asm(lst
, bigendian
))
190 initial_regs
= [0] * 32
191 initial_regs
[1] = 0xc523e996a8ff6215
192 initial_regs
[2] = 0xe1e5b9cc9864c4a8
193 e
= ExpectedState(pc
=4)
194 e
.intregs
[1] = 0xc523e996a8ff6215
195 e
.intregs
[2] = 0xe1e5b9cc9864c4a8
196 e
.intregs
[3] = 0xd384d1b1a0b2135f
197 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
199 def case_1_avgadd(self
):
200 lst
= ["avgadd 3, 1, 2"]
201 lst
= list(SVP64Asm(lst
, bigendian
))
203 initial_regs
= [0] * 32
204 initial_regs
[1] = 0xc523e996a8ff6214
205 initial_regs
[2] = 0xe1e5b9cc9864c4a8
206 e
= ExpectedState(pc
=4)
207 e
.intregs
[1] = 0xc523e996a8ff6214
208 e
.intregs
[2] = 0xe1e5b9cc9864c4a8
209 e
.intregs
[3] = 0xd384d1b1a0b2135e
210 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
212 def case_2_avgadd(self
):
213 lst
= ["avgadd 3, 1, 2"]
214 lst
= list(SVP64Asm(lst
, bigendian
))
216 initial_regs
= [0] * 32
217 initial_regs
[1] = 0xc523e996a8ff6213
218 initial_regs
[2] = 0xe1e5b9cc9864c4a8
219 e
= ExpectedState(pc
=4)
220 e
.intregs
[1] = 0xc523e996a8ff6213
221 e
.intregs
[2] = 0xe1e5b9cc9864c4a8
222 e
.intregs
[3] = 0xd384d1b1a0b2135e
223 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
225 def case_3_avgadd(self
):
226 lst
= ["avgadd 3, 1, 2"]
227 lst
= list(SVP64Asm(lst
, bigendian
))
229 initial_regs
= [0] * 32
230 initial_regs
[1] = 0xffffffffffffffff
231 initial_regs
[2] = 0xffffffffffffffff
232 e
= ExpectedState(pc
=4)
233 e
.intregs
[1] = 0xffffffffffffffff
234 e
.intregs
[2] = 0xffffffffffffffff
235 e
.intregs
[3] = 0xffffffffffffffff
236 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
238 def case_0_absds(self
):
239 lst
= ["absds 3, 1, 2"]
240 lst
= list(SVP64Asm(lst
, bigendian
))
242 initial_regs
= [0] * 32
243 initial_regs
[1] = 0x1
244 initial_regs
[2] = 0x2
245 e
= ExpectedState(pc
=4)
249 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
251 def case_1_absds(self
):
252 lst
= ["absds 3, 1, 2"]
253 lst
= list(SVP64Asm(lst
, bigendian
))
255 initial_regs
= [0] * 32
256 initial_regs
[1] = 0xffffffffffffffff
257 initial_regs
[2] = 0x2
258 e
= ExpectedState(pc
=4)
259 e
.intregs
[1] = 0xffffffffffffffff
262 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
264 def case_0_absdu(self
):
265 lst
= ["absdu 3, 1, 2"]
266 lst
= list(SVP64Asm(lst
, bigendian
))
268 initial_regs
= [0] * 32
269 initial_regs
[1] = 0x1
270 initial_regs
[2] = 0x2
271 e
= ExpectedState(pc
=4)
275 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
277 def case_1_absdu(self
):
278 lst
= ["absdu 3, 1, 2"]
279 lst
= list(SVP64Asm(lst
, bigendian
))
281 initial_regs
= [0] * 32
282 initial_regs
[1] = 0xffffffffffffffff
283 initial_regs
[2] = 0x2
284 e
= ExpectedState(pc
=4)
285 e
.intregs
[1] = 0xffffffffffffffff
287 e
.intregs
[3] = 0xfffffffffffffffd
288 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
290 def case_2_absdu(self
):
291 lst
= ["absdu 3, 1, 2"]
292 lst
= list(SVP64Asm(lst
, bigendian
))
294 initial_regs
= [0] * 32
295 initial_regs
[1] = 0x2
296 initial_regs
[2] = 0xffffffffffffffff
297 e
= ExpectedState(pc
=4)
299 e
.intregs
[2] = 0xffffffffffffffff
300 e
.intregs
[3] = 0xfffffffffffffffd
301 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
303 def case_0_absdacu(self
):
304 lst
= ["absdacu 3, 1, 2",
307 lst
= list(SVP64Asm(lst
, bigendian
))
309 initial_regs
= [0] * 32
310 initial_regs
[1] = 0x2
311 initial_regs
[2] = 0x1
312 initial_regs
[4] = 0x9
313 initial_regs
[5] = 0x3
314 e
= ExpectedState(pc
=8)
320 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
322 def case_1_absdacu(self
):
323 lst
= ["absdacu 3, 1, 2",
326 lst
= list(SVP64Asm(lst
, bigendian
))
328 initial_regs
= [0] * 32
329 initial_regs
[1] = 0x1
330 initial_regs
[2] = 0x2
331 initial_regs
[4] = 0x9
332 initial_regs
[5] = 0x3
333 e
= ExpectedState(pc
=8)
339 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
341 def case_2_absdacu(self
):
342 """weird case where there's a negative number
343 * -1 is greater than 2 (as an unsigned number)
344 therefore difference is (-1)-(2) which is -3
348 * 9 is greater than 3
349 therefore differences is (9)-(3) which is 6
355 lst
= ["absdacu 3, 1, 2",
358 lst
= list(SVP64Asm(lst
, bigendian
))
360 initial_regs
= [0] * 32
361 initial_regs
[1] = 0x2
362 initial_regs
[2] = 0xffffffffffffffff
363 initial_regs
[4] = 0x9
364 initial_regs
[5] = 0x3
365 e
= ExpectedState(pc
=8)
367 e
.intregs
[2] = 0xffffffffffffffff
368 e
.intregs
[3] = 0x3 # ((-1)-(2)) + ((9)-(3))
371 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
373 def case_0_absdacs(self
):
374 lst
= ["absdacs 3, 1, 2",
377 lst
= list(SVP64Asm(lst
, bigendian
))
379 initial_regs
= [0] * 32
380 initial_regs
[1] = 0x2
381 initial_regs
[2] = 0x1
382 initial_regs
[4] = 0x9
383 initial_regs
[5] = 0x3
384 e
= ExpectedState(pc
=8)
390 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
392 def case_2_absdacs(self
):
393 """unlike the absdacu weird case, the 0xfff is treated as signed
394 so (2) < (-1) and the difference is (2--1)=3. next instruction
395 adds 6 more. answer: 9
397 lst
= ["absdacs 3, 1, 2",
400 lst
= list(SVP64Asm(lst
, bigendian
))
402 initial_regs
= [0] * 32
403 initial_regs
[1] = 0x2
404 initial_regs
[2] = 0xffffffffffffffff
405 initial_regs
[4] = 0x9
406 initial_regs
[5] = 0x3
407 e
= ExpectedState(pc
=8)
409 e
.intregs
[2] = 0xffffffffffffffff
413 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
415 def case_0_cprop(self
):
416 lst
= ["cprop 3, 1, 2" ]
417 lst
= list(SVP64Asm(lst
, bigendian
))
423 initial_regs
= [0] * 32
424 initial_regs
[1] = reg_a
425 initial_regs
[2] = reg_b
426 e
= ExpectedState(pc
=last_pc
)
430 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
432 def case_1_cprop(self
):
433 lst
= ["cprop 3, 1, 2" ]
434 lst
= list(SVP64Asm(lst
, bigendian
))
440 initial_regs
= [0] * 32
441 initial_regs
[1] = reg_a
442 initial_regs
[2] = reg_b
443 e
= ExpectedState(pc
=last_pc
)
447 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
449 def case_2_cprop(self
):
450 lst
= ["cprop 3, 1, 2" ]
451 lst
= list(SVP64Asm(lst
, bigendian
))
457 initial_regs
= [0] * 32
458 initial_regs
[1] = reg_a
459 initial_regs
[2] = reg_b
460 e
= ExpectedState(pc
=last_pc
)
464 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
466 def case_0_bmask(self
):
468 https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/bmask.py
469 https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/test_bmask.py
470 https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/av.mdwn;hb=HEAD
471 SBF = 0b01010 # set before first
472 SOF = 0b01001 # set only first
473 SIF = 0b10000 # set including first 10011 also works no idea why yet
475 lst
= ["bmask 3, 1, 2, 10, 0" ]
476 lst
= list(SVP64Asm(lst
, bigendian
))
482 initial_regs
= [0] * 32
483 initial_regs
[1] = reg_a
484 initial_regs
[2] = reg_b
485 e
= ExpectedState(pc
=last_pc
)
489 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
491 def case_1_bmask(self
):
493 SBF = 0b01010 # set before first
494 SOF = 0b01001 # set only first
495 SIF = 0b10000 # set including first 10011 also works no idea why yet
498 bm[0:1] - sets operation 0:OR 1:AND 2:XOR 3:RT=UNDEFINED
499 bm[2:3] - sets second operand: 0:-RA 1:RA-1 2:RA+1 3:~(RA+1)
500 bm[4] - sets the first operand: 0:~RA 1:RA
501 RB - if 0 no mask, otherwise masks RA
503 NOTE: the numbering above for bm[] is in *MSB0* order.
506 lst
= ["bmask 3, 1, 2, 3, 0", # OR : RA | (RA-1) 00 01 1
507 "bmask 4, 1, 2, 11, 0", # AND : RA & (RA-1) 01 01 1
508 "bmask 5, 1, 2, 19, 0", # XOR : RA ^ (RA-1) 10 01 1
509 "bmask 6, 1, 2, 27, 0", # 0 : 0
511 lst
= list(SVP64Asm(lst
, bigendian
))
520 initial_regs
= [0] * 32
521 initial_regs
[1] = reg_a
522 initial_regs
[2] = reg_b
523 e
= ExpectedState(pc
=last_pc
)
526 e
.intregs
[3] = reg_t0
527 e
.intregs
[4] = reg_t1
528 e
.intregs
[5] = reg_t2
529 e
.intregs
[6] = reg_t3
530 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
532 def case_2_bmask(self
):
534 SBF = 0b01010 # set before first
535 SOF = 0b01001 # set only first
536 SIF = 0b10000 # set including first 10011 also works no idea why yet
539 lst
= ["bmask 3, 1, 2, 16, 0",]
540 # "bmask 6, 4, 5, 16, 0",
541 # "bmask 9, 7, 8, 16, 0",
542 # "bmask 12, 10, 11, 16, 0",
544 lst
= list(SVP64Asm(lst
, bigendian
))
547 initial_regs
= [0] * 32
548 e
= ExpectedState(pc
=last_pc
)
551 v3
= 0b10010100 # vmsif.m v2, v3
559 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)
561 def case_3_bmask(self
):
563 SBF = 0b01010 # set before first
564 SOF = 0b01001 # set only first
565 SIF = 0b10000 # set including first 10011 also works no idea why yet
568 lst
= ["bmask 3, 1, 2, 9, 0",]
569 lst
= list(SVP64Asm(lst
, bigendian
))
572 initial_regs
= [0] * 32
573 e
= ExpectedState(pc
=last_pc
)
576 v3
= 0b11010100 # vmsof.m v2, v3
583 self
.add_case(Program(lst
, bigendian
), initial_regs
, expected
=e
)