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pysvp64asm: integrate into insndb
[openpower-isa.git] / src / openpower / test / bitmanip / av_cases.py
1 from openpower.insndb.asm import SVP64Asm
2 import random
3 from openpower.test.common import TestAccumulatorBase
4 from openpower.endian import bigendian
5 from openpower.simulator.program import Program
6 from openpower.decoder.selectable_int import SelectableInt
7 from openpower.decoder.power_enums import XER_bits
8 from openpower.decoder.isa.caller import special_sprs
9 from openpower.decoder.helpers import exts
10 from openpower.test.state import ExpectedState
11 import unittest
12
13
14 class AVTestCase(TestAccumulatorBase):
15
16 def case_0_maxs(self):
17 lst = ["minmax 3, 1, 2, 3"]
18 lst = list(SVP64Asm(lst, bigendian))
19
20 initial_regs = [0] * 32
21 initial_regs[1] = 0xc523e996a8ff6215
22 initial_regs[2] = 0xe1e5b9cc9864c4a8
23 e = ExpectedState(pc=4)
24 e.intregs[1] = 0xc523e996a8ff6215
25 e.intregs[2] = 0xe1e5b9cc9864c4a8
26 e.intregs[3] = 0xe1e5b9cc9864c4a8
27 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
28
29 def case_1_maxs(self):
30 lst = ["minmax 3, 1, 2, 3"]
31 lst = list(SVP64Asm(lst, bigendian))
32
33 initial_regs = [0] * 32
34 initial_regs[1] = 0xe1e5b9cc9864c4a8
35 initial_regs[2] = 0xc523e996a8ff6215
36 e = ExpectedState(pc=4)
37 e.intregs[1] = 0xe1e5b9cc9864c4a8
38 e.intregs[2] = 0xc523e996a8ff6215
39 e.intregs[3] = 0xe1e5b9cc9864c4a8
40 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
41
42 def case_2_maxs_(self):
43 lst = [f"minmax. 3, 1, 2, 3"]
44 lst = list(SVP64Asm(lst, bigendian))
45
46 initial_regs = [0] * 32
47 initial_regs[1] = 0xc523e996a8ff6215
48 initial_regs[2] = 0xe1e5b9cc9864c4a8
49 e = ExpectedState(pc=4)
50 e.intregs[1] = 0xc523e996a8ff6215
51 e.intregs[2] = 0xe1e5b9cc9864c4a8
52 e.intregs[3] = 0xe1e5b9cc9864c4a8
53 e.crregs[0] = 0x8
54 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
55
56 def case_3_maxs_(self):
57 lst = [f"minmax. 3, 1, 2, 3"]
58 lst = list(SVP64Asm(lst, bigendian))
59
60 initial_regs = [0] * 32
61 initial_regs[1] = 0xc523e996a8ff6215
62 initial_regs[2] = 0
63 e = ExpectedState(pc=4)
64 e.intregs[1] = 0xc523e996a8ff6215
65 e.intregs[2] = 0
66 e.intregs[3] = 0
67 e.crregs[0] = 0x8 # RB greater (arithmeticslly)
68 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
69
70 def case_4_maxs_(self):
71 lst = [f"minmax. 3, 1, 2, 3"]
72 lst = list(SVP64Asm(lst, bigendian))
73
74 initial_regs = [0] * 32
75 initial_regs[1] = 1
76 initial_regs[2] = 0
77 e = ExpectedState(pc=4)
78 e.intregs[1] = 1
79 e.intregs[2] = 0
80 e.intregs[3] = 1
81 e.crregs[0] = 0x4 # RT is +ve
82 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
83
84 def case_5_maxs_(self):
85 """max negative number compared against +ve number
86 """
87 lst = [f"minmax. 3, 1, 2, 3"]
88 lst = list(SVP64Asm(lst, bigendian))
89
90 initial_regs = [0] * 32
91 initial_regs[1] = 1
92 initial_regs[2] = 0x8000_0000_0000_0000
93 e = ExpectedState(pc=4)
94 e.intregs[1] = 1
95 e.intregs[2] = 0x8000_0000_0000_0000
96 e.intregs[3] = 1
97 e.crregs[0] = 0x4 # RT is +ve
98 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
99
100 def case_6_maxs_(self):
101 lst = [f"minmax. 3, 1, 2, 3"]
102 lst = list(SVP64Asm(lst, bigendian))
103
104 initial_regs = [0] * 32
105 initial_regs[1] = 0x8000_0000_0000_0000
106 initial_regs[2] = 0x8000_0000_0000_0000
107 e = ExpectedState(pc=4)
108 e.intregs[1] = 0x8000_0000_0000_0000
109 e.intregs[2] = 0x8000_0000_0000_0000
110 e.intregs[3] = 0x8000_0000_0000_0000
111 e.crregs[0] = 0x2 # values are equal
112 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
113
114 def case_0_mins(self):
115 lst = ["minmax 3, 1, 2, 2"]
116 lst = list(SVP64Asm(lst, bigendian))
117
118 initial_regs = [0] * 32
119 initial_regs[1] = 0xc523e996a8ff6215
120 initial_regs[2] = 0xe1e5b9cc9864c4a8
121 e = ExpectedState(pc=4)
122 e.intregs[1] = 0xc523e996a8ff6215
123 e.intregs[2] = 0xe1e5b9cc9864c4a8
124 e.intregs[3] = 0xc523e996a8ff6215
125 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
126
127 def case_2_mins_(self):
128 lst = [f"minmax. 3, 1, 2, 2"]
129 lst = list(SVP64Asm(lst, bigendian))
130
131 initial_regs = [0] * 32
132 initial_regs[1] = 0xc523e996a8ff6215
133 initial_regs[2] = 0xe1e5b9cc9864c4a8
134 e = ExpectedState(pc=4)
135 e.intregs[1] = 0xc523e996a8ff6215
136 e.intregs[2] = 0xe1e5b9cc9864c4a8
137 e.intregs[3] = 0xc523e996a8ff6215
138 e.crregs[0] = 0x8
139 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
140
141 def case_5_mins_(self):
142 """min negative number compared against +ve number
143 """
144 lst = [f"minmax. 3, 1, 2, 2"]
145 lst = list(SVP64Asm(lst, bigendian))
146
147 initial_regs = [0] * 32
148 initial_regs[1] = 1
149 initial_regs[2] = 0x8000_0000_0000_0000
150 e = ExpectedState(pc=4)
151 e.intregs[1] = 1
152 e.intregs[2] = 0x8000_0000_0000_0000
153 e.intregs[3] = 0x8000_0000_0000_0000
154 e.crregs[0] = 0x4 # r1 >s r2
155 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
156
157 def case_0_maxu(self):
158 lst = ["minmax 3, 1, 2, 1"]
159 lst = list(SVP64Asm(lst, bigendian))
160
161 initial_regs = [0] * 32
162 initial_regs[1] = 0xc523e996a8ff6215
163 initial_regs[2] = 0xe1e5b9cc9864c4a8
164 e = ExpectedState(pc=4)
165 e.intregs[1] = 0xc523e996a8ff6215
166 e.intregs[2] = 0xe1e5b9cc9864c4a8
167 e.intregs[3] = 0xe1e5b9cc9864c4a8
168 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
169
170 def case_5_minu_(self):
171 """min +ve numbers
172 """
173 lst = [f"minmax. 3, 1, 2, 0"]
174 lst = list(SVP64Asm(lst, bigendian))
175
176 initial_regs = [0] * 32
177 initial_regs[1] = 1
178 initial_regs[2] = 0x8000_0000_0000_0000
179 e = ExpectedState(pc=4)
180 e.intregs[1] = 1
181 e.intregs[2] = 0x8000_0000_0000_0000
182 e.intregs[3] = min(e.intregs[1], e.intregs[2])
183 e.crregs[0] = 0x8 # r1 <u r2
184 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
185
186 def case_0_avgadd(self):
187 lst = ["avgadd 3, 1, 2"]
188 lst = list(SVP64Asm(lst, bigendian))
189
190 initial_regs = [0] * 32
191 initial_regs[1] = 0xc523e996a8ff6215
192 initial_regs[2] = 0xe1e5b9cc9864c4a8
193 e = ExpectedState(pc=4)
194 e.intregs[1] = 0xc523e996a8ff6215
195 e.intregs[2] = 0xe1e5b9cc9864c4a8
196 e.intregs[3] = 0xd384d1b1a0b2135f
197 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
198
199 def case_1_avgadd(self):
200 lst = ["avgadd 3, 1, 2"]
201 lst = list(SVP64Asm(lst, bigendian))
202
203 initial_regs = [0] * 32
204 initial_regs[1] = 0xc523e996a8ff6214
205 initial_regs[2] = 0xe1e5b9cc9864c4a8
206 e = ExpectedState(pc=4)
207 e.intregs[1] = 0xc523e996a8ff6214
208 e.intregs[2] = 0xe1e5b9cc9864c4a8
209 e.intregs[3] = 0xd384d1b1a0b2135e
210 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
211
212 def case_2_avgadd(self):
213 lst = ["avgadd 3, 1, 2"]
214 lst = list(SVP64Asm(lst, bigendian))
215
216 initial_regs = [0] * 32
217 initial_regs[1] = 0xc523e996a8ff6213
218 initial_regs[2] = 0xe1e5b9cc9864c4a8
219 e = ExpectedState(pc=4)
220 e.intregs[1] = 0xc523e996a8ff6213
221 e.intregs[2] = 0xe1e5b9cc9864c4a8
222 e.intregs[3] = 0xd384d1b1a0b2135e
223 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
224
225 def case_3_avgadd(self):
226 lst = ["avgadd 3, 1, 2"]
227 lst = list(SVP64Asm(lst, bigendian))
228
229 initial_regs = [0] * 32
230 initial_regs[1] = 0xffffffffffffffff
231 initial_regs[2] = 0xffffffffffffffff
232 e = ExpectedState(pc=4)
233 e.intregs[1] = 0xffffffffffffffff
234 e.intregs[2] = 0xffffffffffffffff
235 e.intregs[3] = 0xffffffffffffffff
236 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
237
238 def case_0_absds(self):
239 lst = ["absds 3, 1, 2"]
240 lst = list(SVP64Asm(lst, bigendian))
241
242 initial_regs = [0] * 32
243 initial_regs[1] = 0x1
244 initial_regs[2] = 0x2
245 e = ExpectedState(pc=4)
246 e.intregs[1] = 0x1
247 e.intregs[2] = 0x2
248 e.intregs[3] = 0x1
249 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
250
251 def case_1_absds(self):
252 lst = ["absds 3, 1, 2"]
253 lst = list(SVP64Asm(lst, bigendian))
254
255 initial_regs = [0] * 32
256 initial_regs[1] = 0xffffffffffffffff
257 initial_regs[2] = 0x2
258 e = ExpectedState(pc=4)
259 e.intregs[1] = 0xffffffffffffffff
260 e.intregs[2] = 0x2
261 e.intregs[3] = 0x3
262 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
263
264 def case_0_absdu(self):
265 lst = ["absdu 3, 1, 2"]
266 lst = list(SVP64Asm(lst, bigendian))
267
268 initial_regs = [0] * 32
269 initial_regs[1] = 0x1
270 initial_regs[2] = 0x2
271 e = ExpectedState(pc=4)
272 e.intregs[1] = 0x1
273 e.intregs[2] = 0x2
274 e.intregs[3] = 0x1
275 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
276
277 def case_1_absdu(self):
278 lst = ["absdu 3, 1, 2"]
279 lst = list(SVP64Asm(lst, bigendian))
280
281 initial_regs = [0] * 32
282 initial_regs[1] = 0xffffffffffffffff
283 initial_regs[2] = 0x2
284 e = ExpectedState(pc=4)
285 e.intregs[1] = 0xffffffffffffffff
286 e.intregs[2] = 0x2
287 e.intregs[3] = 0xfffffffffffffffd
288 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
289
290 def case_2_absdu(self):
291 lst = ["absdu 3, 1, 2"]
292 lst = list(SVP64Asm(lst, bigendian))
293
294 initial_regs = [0] * 32
295 initial_regs[1] = 0x2
296 initial_regs[2] = 0xffffffffffffffff
297 e = ExpectedState(pc=4)
298 e.intregs[1] = 0x2
299 e.intregs[2] = 0xffffffffffffffff
300 e.intregs[3] = 0xfffffffffffffffd
301 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
302
303 def case_0_absdacu(self):
304 lst = ["absdacu 3, 1, 2",
305 "absdacu 3, 4, 5",
306 ]
307 lst = list(SVP64Asm(lst, bigendian))
308
309 initial_regs = [0] * 32
310 initial_regs[1] = 0x2
311 initial_regs[2] = 0x1
312 initial_regs[4] = 0x9
313 initial_regs[5] = 0x3
314 e = ExpectedState(pc=8)
315 e.intregs[1] = 0x2
316 e.intregs[2] = 0x1
317 e.intregs[3] = 0x7
318 e.intregs[4] = 0x9
319 e.intregs[5] = 0x3
320 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
321
322 def case_1_absdacu(self):
323 lst = ["absdacu 3, 1, 2",
324 "absdacu 3, 4, 5",
325 ]
326 lst = list(SVP64Asm(lst, bigendian))
327
328 initial_regs = [0] * 32
329 initial_regs[1] = 0x1
330 initial_regs[2] = 0x2
331 initial_regs[4] = 0x9
332 initial_regs[5] = 0x3
333 e = ExpectedState(pc=8)
334 e.intregs[1] = 0x1
335 e.intregs[2] = 0x2
336 e.intregs[3] = 0x7
337 e.intregs[4] = 0x9
338 e.intregs[5] = 0x3
339 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
340
341 def case_2_absdacu(self):
342 """weird case where there's a negative number
343 * -1 is greater than 2 (as an unsigned number)
344 therefore difference is (-1)-(2) which is -3
345 RT=RT+-3
346 =0-3
347 =-3
348 * 9 is greater than 3
349 therefore differences is (9)-(3) which is 6
350 RT=RT+6
351 =-3+6
352 =3
353 * answer: RT=3
354 """
355 lst = ["absdacu 3, 1, 2",
356 "absdacu 3, 4, 5",
357 ]
358 lst = list(SVP64Asm(lst, bigendian))
359
360 initial_regs = [0] * 32
361 initial_regs[1] = 0x2
362 initial_regs[2] = 0xffffffffffffffff
363 initial_regs[4] = 0x9
364 initial_regs[5] = 0x3
365 e = ExpectedState(pc=8)
366 e.intregs[1] = 0x2
367 e.intregs[2] = 0xffffffffffffffff
368 e.intregs[3] = 0x3 # ((-1)-(2)) + ((9)-(3))
369 e.intregs[4] = 0x9
370 e.intregs[5] = 0x3
371 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
372
373 def case_0_absdacs(self):
374 lst = ["absdacs 3, 1, 2",
375 "absdacs 3, 4, 5",
376 ]
377 lst = list(SVP64Asm(lst, bigendian))
378
379 initial_regs = [0] * 32
380 initial_regs[1] = 0x2
381 initial_regs[2] = 0x1
382 initial_regs[4] = 0x9
383 initial_regs[5] = 0x3
384 e = ExpectedState(pc=8)
385 e.intregs[1] = 0x2
386 e.intregs[2] = 0x1
387 e.intregs[3] = 0x7
388 e.intregs[4] = 0x9
389 e.intregs[5] = 0x3
390 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
391
392 def case_2_absdacs(self):
393 """unlike the absdacu weird case, the 0xfff is treated as signed
394 so (2) < (-1) and the difference is (2--1)=3. next instruction
395 adds 6 more. answer: 9
396 """
397 lst = ["absdacs 3, 1, 2",
398 "absdacs 3, 4, 5",
399 ]
400 lst = list(SVP64Asm(lst, bigendian))
401
402 initial_regs = [0] * 32
403 initial_regs[1] = 0x2
404 initial_regs[2] = 0xffffffffffffffff
405 initial_regs[4] = 0x9
406 initial_regs[5] = 0x3
407 e = ExpectedState(pc=8)
408 e.intregs[1] = 0x2
409 e.intregs[2] = 0xffffffffffffffff
410 e.intregs[3] = 9
411 e.intregs[4] = 0x9
412 e.intregs[5] = 0x3
413 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
414
415 def case_0_cprop(self):
416 lst = ["cprop 3, 1, 2" ]
417 lst = list(SVP64Asm(lst, bigendian))
418 last_pc = len(lst)*4
419 reg_a = 0b000001
420 reg_b = 0b000111
421 reg_t = 0b001111
422
423 initial_regs = [0] * 32
424 initial_regs[1] = reg_a
425 initial_regs[2] = reg_b
426 e = ExpectedState(pc=last_pc)
427 e.intregs[1] = reg_a
428 e.intregs[2] = reg_b
429 e.intregs[3] = reg_t
430 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
431
432 def case_1_cprop(self):
433 lst = ["cprop 3, 1, 2" ]
434 lst = list(SVP64Asm(lst, bigendian))
435 last_pc = len(lst)*4
436 reg_a = 0b000010
437 reg_b = 0b001111
438 reg_t = 0b011100
439
440 initial_regs = [0] * 32
441 initial_regs[1] = reg_a
442 initial_regs[2] = reg_b
443 e = ExpectedState(pc=last_pc)
444 e.intregs[1] = reg_a
445 e.intregs[2] = reg_b
446 e.intregs[3] = reg_t
447 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
448
449 def case_2_cprop(self):
450 lst = ["cprop 3, 1, 2" ]
451 lst = list(SVP64Asm(lst, bigendian))
452 last_pc = len(lst)*4
453 reg_a = 0b000010
454 reg_b = 0b001110
455 reg_t = 0b011110
456
457 initial_regs = [0] * 32
458 initial_regs[1] = reg_a
459 initial_regs[2] = reg_b
460 e = ExpectedState(pc=last_pc)
461 e.intregs[1] = reg_a
462 e.intregs[2] = reg_b
463 e.intregs[3] = reg_t
464 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
465
466 def case_0_bmask(self):
467 """
468 https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/bmask.py
469 https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/test_bmask.py
470 https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/av.mdwn;hb=HEAD
471 SBF = 0b01010 # set before first
472 SOF = 0b01001 # set only first
473 SIF = 0b10000 # set including first 10011 also works no idea why yet
474 """
475 lst = ["bmask 3, 1, 2, 10, 0" ]
476 lst = list(SVP64Asm(lst, bigendian))
477 last_pc = len(lst)*4
478 reg_a = 0b10010100
479 reg_b = 0b11000011
480 reg_t = 0b01000011
481
482 initial_regs = [0] * 32
483 initial_regs[1] = reg_a
484 initial_regs[2] = reg_b
485 e = ExpectedState(pc=last_pc)
486 e.intregs[1] = reg_a
487 e.intregs[2] = reg_b
488 e.intregs[3] = reg_t
489 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
490
491 def case_1_bmask(self):
492 """
493 SBF = 0b01010 # set before first
494 SOF = 0b01001 # set only first
495 SIF = 0b10000 # set including first 10011 also works no idea why yet
496
497 bmask RT,RA,RB,bm,L
498 bm[0:1] - sets operation 0:OR 1:AND 2:XOR 3:RT=UNDEFINED
499 bm[2:3] - sets second operand: 0:-RA 1:RA-1 2:RA+1 3:~(RA+1)
500 bm[4] - sets the first operand: 0:~RA 1:RA
501 RB - if 0 no mask, otherwise masks RA
502
503 NOTE: the numbering above for bm[] is in *MSB0* order.
504 """
505
506 lst = ["bmask 3, 1, 2, 3, 0", # OR : RA | (RA-1) 00 01 1
507 "bmask 4, 1, 2, 11, 0", # AND : RA & (RA-1) 01 01 1
508 "bmask 5, 1, 2, 19, 0", # XOR : RA ^ (RA-1) 10 01 1
509 "bmask 6, 1, 2, 27, 0", # 0 : 0
510 ]
511 lst = list(SVP64Asm(lst, bigendian))
512 last_pc = len(lst)*4
513 reg_a = 0b10010100
514 reg_b = 0b11000011
515 reg_t0 = 0b11000011
516 reg_t1 = 0b00000000
517 reg_t2 = 0b11000011
518 reg_t3 = 0b00000000
519
520 initial_regs = [0] * 32
521 initial_regs[1] = reg_a
522 initial_regs[2] = reg_b
523 e = ExpectedState(pc=last_pc)
524 e.intregs[1] = reg_a
525 e.intregs[2] = reg_b
526 e.intregs[3] = reg_t0
527 e.intregs[4] = reg_t1
528 e.intregs[5] = reg_t2
529 e.intregs[6] = reg_t3
530 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
531
532 def case_2_bmask(self):
533 """
534 SBF = 0b01010 # set before first
535 SOF = 0b01001 # set only first
536 SIF = 0b10000 # set including first 10011 also works no idea why yet
537 """
538 #SIF
539 lst = ["bmask 3, 1, 2, 16, 0",]
540 # "bmask 6, 4, 5, 16, 0",
541 # "bmask 9, 7, 8, 16, 0",
542 # "bmask 12, 10, 11, 16, 0",
543 #]
544 lst = list(SVP64Asm(lst, bigendian))
545 last_pc = len(lst)*4
546
547 initial_regs = [0] * 32
548 e = ExpectedState(pc=last_pc)
549
550 m = 0b11000011
551 v3 = 0b10010100 # vmsif.m v2, v3
552 v2 = 0b11000011 # v2
553 initial_regs[1] = v3
554 initial_regs[2] = m
555 e.intregs[1] = v3
556 e.intregs[2] = m
557 e.intregs[3] = v2
558
559 self.add_case(Program(lst, bigendian), initial_regs, expected=e)
560
561 def case_3_bmask(self):
562 """
563 SBF = 0b01010 # set before first
564 SOF = 0b01001 # set only first
565 SIF = 0b10000 # set including first 10011 also works no idea why yet
566 """
567 #SOF
568 lst = ["bmask 3, 1, 2, 9, 0",]
569 lst = list(SVP64Asm(lst, bigendian))
570 last_pc = len(lst)*4
571
572 initial_regs = [0] * 32
573 e = ExpectedState(pc=last_pc)
574
575 m = 0b11000011
576 v3 = 0b11010100 # vmsof.m v2, v3
577 v2 = 0b01000000 # v2
578 initial_regs[1] = v3
579 initial_regs[2] = m
580 e.intregs[1] = v3
581 e.intregs[2] = m
582 e.intregs[3] = v2
583 self.add_case(Program(lst, bigendian), initial_regs, expected=e)