src/openpower/test/bitmanip/bitmanip_cases.py

   1 from openpower.sv.trans.svp64 import SVP64Asm
   2 from openpower.test.common import TestAccumulatorBase, skip_case
   3 from openpower.endian import bigendian
   4 from openpower.simulator.program import Program
   5 from openpower.test.state import ExpectedState
   6 from nmutil.sim_util import hash_256
   7
   8
   9 class BitManipTestCase(TestAccumulatorBase):
  10     def do_case_ternlogi(self, rc, rt, ra, rb, imm):
  11         rc_dot = "." if rc else ""
  12         lst = [f"ternlogi{rc_dot} 3, 4, 5, {imm}"]
  13         initial_regs = [0] * 32
  14         rt %= 2 ** 64
  15         ra %= 2 ** 64
  16         rb %= 2 ** 64
  17         initial_regs[3] = rt
  18         initial_regs[4] = ra
  19         initial_regs[5] = rb
  20         lst = list(SVP64Asm(lst, bigendian))
  21         e = ExpectedState(pc=4)
  22         expected = 0
  23         for i in range(64):
  24             lut_index = 0
  25             if rb & 2 ** i:
  26                 lut_index |= 2 ** 0
  27             if ra & 2 ** i:
  28                 lut_index |= 2 ** 1
  29             if rt & 2 ** i:
  30                 lut_index |= 2 ** 2
  31             if imm & 2 ** lut_index:
  32                 expected |= 2 ** i
  33         e.intregs[3] = expected
  34         e.intregs[4] = ra
  35         e.intregs[5] = rb
  36         if rc:
  37             if expected & 2 ** 63:  # sign extend
  38                 expected -= 2 ** 64
  39             eq = expected == 0
  40             gt = expected > 0
  41             lt = expected < 0
  42             e.crregs[0] = (eq << 1) | (gt << 2) | (lt << 3)
  43         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  44
  45     def do_case_grev(self, w, is_imm, ra, rb):
  46         bits = 32 if w else 64
  47         masked_rb = rb % bits
  48         if is_imm:
  49             lst = [f"grev{'w' if w else ''}i. 3, 4, {masked_rb}"]
  50         else:
  51             lst = [f"grev{'w' if w else ''}. 3, 4, 5"]
  52         initial_regs = [0] * 32
  53         ra %= 2 ** 64
  54         rb %= 2 ** 64
  55         initial_regs[4] = ra
  56         initial_regs[5] = rb
  57         lst = list(SVP64Asm(lst, bigendian))
  58         e = ExpectedState(pc=4)
  59         expected = 0
  60         for i in range(bits):
  61             dest_bit = i ^ masked_rb
  62             if ra & 2 ** i:
  63                 expected |= 2 ** dest_bit
  64         e.intregs[3] = expected
  65         e.intregs[4] = ra
  66         e.intregs[5] = rb
  67         if expected & 2 ** 63:  # sign extend
  68             expected -= 2 ** 64
  69         eq = expected == 0
  70         gt = expected > 0
  71         lt = expected < 0
  72         e.crregs[0] = (eq << 1) | (gt << 2) | (lt << 3)
  73         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  74
  75     def case_ternlogi_0(self):
  76         self.do_case_ternlogi(False,
  77                               0x8000_0000_FFFF_0000,
  78                               0x8000_0000_FF00_FF00,
  79                               0x8000_0000_F0F0_F0F0, 0x80)
  80         self.do_case_ternlogi(True,
  81                               0x8000_0000_FFFF_0000,
  82                               0x8000_0000_FF00_FF00,
  83                               0x8000_0000_F0F0_F0F0, 0x80)
  84
  85     def case_ternlogi_FF(self):
  86         self.do_case_ternlogi(False, 0, 0, 0, 0xFF)
  87         self.do_case_ternlogi(True, 0, 0, 0, 0xFF)
  88
  89     def case_ternlogi_random(self):
  90         for i in range(100):
  91             rc = bool(hash_256(f"ternlogi rc {i}") & 1)
  92             imm = hash_256(f"ternlogi imm {i}") & 0xFF
  93             rt = hash_256(f"ternlogi rt {i}") % 2 ** 64
  94             ra = hash_256(f"ternlogi ra {i}") % 2 ** 64
  95             rb = hash_256(f"ternlogi rb {i}") % 2 ** 64
  96             self.do_case_ternlogi(rc, rt, ra, rb, imm)
  97
  98     @skip_case("invalid, replaced by grevlut")
  99     def case_grev_random(self):
 100         for i in range(100):
 101             w = hash_256(f"grev w {i}") & 1
 102             is_imm = hash_256(f"grev is_imm {i}") & 1
 103             ra = hash_256(f"grev ra {i}") % 2 ** 64
 104             rb = hash_256(f"grev rb {i}") % 2 ** 64
 105             self.do_case_grev(w, is_imm, ra, rb)
 106
 107     @skip_case("invalid, replaced by grevlut")
 108     def case_grevi_1(self):
 109         self.do_case_grev(False, True, 14361919363078703450,
 110                           8396479064514513069)
 111
 112     @skip_case("invalid, replaced by grevlut")
 113     def case_grevi_2(self):
 114         self.do_case_grev(True, True, 397097147229333315, 8326716970539357702)
 115
 116     @skip_case("invalid, replaced by grevlut")
 117     def case_grevi_3(self):
 118         self.do_case_grev(True, True, 0xFFFF_FFFF_0000_0000, 6)