src/openpower/test/bitmanip/bitmanip_cases.py

   1 from openpower.sv.trans.svp64 import SVP64Asm
   2 from openpower.test.common import TestAccumulatorBase, skip_case
   3 from openpower.endian import bigendian
   4 from openpower.simulator.program import Program
   5 from openpower.test.state import ExpectedState
   6 from nmutil.sim_util import hash_256
   7
   8
   9 class BitManipTestCase(TestAccumulatorBase):
  10     def do_case_ternlogi(self, rt, ra, rb, imm):
  11         lst = [f"ternlogi 3, 4, 5, {imm}"]
  12         initial_regs = [0] * 32
  13         rt %= 2 ** 64
  14         ra %= 2 ** 64
  15         rb %= 2 ** 64
  16         initial_regs[3] = rt
  17         initial_regs[4] = ra
  18         initial_regs[5] = rb
  19         lst = list(SVP64Asm(lst, bigendian))
  20         e = ExpectedState(pc=4)
  21         expected = 0
  22         for i in range(64):
  23             lut_index = 0
  24             if rb & 2 ** i:
  25                 lut_index |= 2 ** 0
  26             if ra & 2 ** i:
  27                 lut_index |= 2 ** 1
  28             if rt & 2 ** i:
  29                 lut_index |= 2 ** 2
  30             if imm & 2 ** lut_index:
  31                 expected |= 2 ** i
  32         e.intregs[3] = expected
  33         e.intregs[4] = ra
  34         e.intregs[5] = rb
  35         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  36
  37     def case_ternlogi_0(self):
  38         self.do_case_ternlogi(0x8000_0000_FFFF_0000,
  39                               0x8000_0000_FF00_FF00,
  40                               0x8000_0000_F0F0_F0F0, 0x80)
  41
  42     def case_ternlogi_FF(self):
  43         self.do_case_ternlogi(0, 0, 0, 0xFF)
  44
  45     def case_ternlogi_random(self):
  46         for i in range(100):
  47             imm = hash_256(f"ternlogi imm {i}") & 0xFF
  48             rt = hash_256(f"ternlogi rt {i}") % 2 ** 64
  49             ra = hash_256(f"ternlogi ra {i}") % 2 ** 64
  50             rb = hash_256(f"ternlogi rb {i}") % 2 ** 64
  51             self.do_case_ternlogi(rt, ra, rb, imm)