src/openpower/test/mmu/mmu_cases.py

   1 from openpower.simulator.program import Program
   2 from openpower.endian import bigendian
   3 from openpower.consts import MSR
   4
   5
   6 from openpower.test.common import TestAccumulatorBase, skip_case
   7 import random
   8
   9
  10 #incomplete test - connect fsm inputs first
  11 class MMUTestCase(TestAccumulatorBase):
  12     # MMU handles MTSPR, MFSPR, DCBZ and TLBIE.
  13     # other instructions here -> must be load/store
  14
  15     #before running the test case: set DISR and DAR
  16
  17     def case_mfspr_after_invalid_load(self):
  18         lst = [ # TODO -- set SPR on both simulator and port interface
  19                 "mfspr 1, 18", # DSISR to reg 1
  20                 "mfspr 2, 19", # DAR to reg 2
  21                 # TODO -- verify returned sprvals
  22               ]
  23
  24         initial_regs = [0] * 32
  25
  26         initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321}
  27         self.add_case(Program(lst, bigendian),
  28                       initial_regs, initial_sprs)
  29