src/openpower/test/mmu/mmu_rom_cases.py

   1 from openpower.simulator.program import Program
   2 from openpower.endian import bigendian
   3 from openpower.test.common import (TestAccumulatorBase, skip_case)
   4
   5 def b(x):
   6     return int.from_bytes(x.to_bytes(8, byteorder='little'),
   7                           byteorder='big', signed=False)
   8
   9
  10 default_mem = { 0x10000:    # PARTITION_TABLE_2
  11                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
  12                 b(0x800000000100000b),
  13
  14                 0x30000:     # RADIX_ROOT_PTE
  15                         # V = 1 L = 0 NLB = 0x400 NLS = 9
  16                 b(0x8000000000040009),
  17
  18                 0x40000:     # RADIX_SECOND_LEVEL
  19                         #          V = 1 L = 1 SW = 0 RPN = 0
  20                            # R = 1 C = 1 ATT = 0 EAA 0x7
  21                 b(0xc000000000000187),
  22
  23                 0x1000000:   # PROCESS_TABLE_3
  24                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
  25                 b(0x40000000000300ad),
  26             }
  27
  28
  29 class MMUTestCaseROM(TestAccumulatorBase):
  30     # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE.
  31     # libre-soc has own SPR unit
  32     # libre-soc MMU supports MTSPR and MFSPR but **ONLY** for the subset
  33     # of SPRs it actually does.
  34     # other instructions here -> must be load/store
  35
  36     def case_mmu_ldst(self):
  37         lst = [
  38                 #"mtspr 720, 1", # XXX do not execute unsupported instructions
  39                 "lhz 3, 0(1)"      # load some data
  40               ]
  41
  42         initial_regs = [0] * 32
  43
  44         # set process table
  45         prtbl = 0x1000000
  46         initial_regs[1] = prtbl
  47
  48         initial_sprs = {'DSISR': 0, 'DAR': 0,
  49                          720: 0}
  50         self.add_case(Program(lst, bigendian),
  51                       initial_regs, initial_sprs)
  52
  53