src/openpower/test/runner.py

   1 # SPDX-License-Identifier: LGPL-2-or-later
   2 """TestRunner class, part of the Test API
   3
   4 SPDX-License: LGPLv2+
   5
   6 Copyright (C) 2020,2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   7 Copyright (C) 2021 Kyle Lehman <klehman9@comcast.net>
   8 Copyright (C) 2021 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
   9 Copyright (C) 2021 Tobias Platen <tplaten@posteo.de>
  10 Copyright (C) 2021 Cesar Strauss <cestrauss@gmail.com>
  11
  12 related bugs:
  13
  14  * https://bugs.libre-soc.org/show_bug.cgi?id=363
  15  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
  16 """
  17
  18 from unittest.mock import Mock
  19 from nmigen import Module, ClockSignal
  20 from copy import copy, deepcopy
  21 from pprint import pformat
  22
  23 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  24 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  25 from nmutil.sim_tmp_alternative import Simulator, Settle
  26
  27 from nmutil.formaltest import FHDLTestCase
  28 from nmutil.gtkw import write_gtkw
  29 from openpower.decoder.isa.all import ISA
  30 from openpower.endian import bigendian
  31
  32 from openpower.decoder.power_decoder2 import PowerDecode2
  33
  34 from nmutil.util import wrap
  35 from openpower.test.wb_get import wb_get
  36 import openpower.test.wb_get as wbget
  37 from openpower.test.state import TestState, StateRunner, ExpectedState
  38 from openpower.util import log, LogType
  39
  40
  41 class SimRunner(StateRunner):
  42     """SimRunner:  Implements methods for the setup, preparation, and
  43     running of tests using ISACaller simulation
  44     """
  45
  46     def __init__(self, dut, m, pspec,
  47             use_mmap_mem=False,
  48             use_syscall_emu=False):
  49         super().__init__("sim", SimRunner)
  50         self.dut = dut
  51
  52         self.mmu = pspec.mmu == True
  53         fp_en = pspec.fp_en == True
  54         regreduce_en = pspec.regreduce_en == True
  55         self.simdec2 = simdec2 = PowerDecode2(
  56             None, regreduce_en=regreduce_en, fp_en=fp_en)
  57         m.submodules.simdec2 = simdec2  # pain in the neck
  58         self.use_mmap_mem = use_mmap_mem
  59         self.use_syscall_emu = use_syscall_emu
  60
  61     def prepare_for_test(self, test):
  62         self.test = test
  63         if False:
  64             yield
  65
  66     def run_test(self, instructions, gen, insncode):
  67         """run_sim_state - runs an ISACaller simulation
  68         """
  69
  70         dut, test, simdec2 = self.dut, self.test, self.simdec2
  71         sim_states = []
  72
  73         # set up the Simulator (which must track TestIssuer exactly)
  74         sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
  75                   test.msr,
  76                   initial_insns=gen, respect_pc=True,
  77                   disassembly=insncode,
  78                   bigendian=bigendian,
  79                   initial_svstate=test.svstate,
  80                   mmu=self.mmu,
  81                   fpregfile=test.fpregs,
  82                   initial_fpscr=test.initial_fpscr,
  83                   use_mmap_mem=self.use_mmap_mem,
  84                   use_syscall_emu=self.use_syscall_emu)
  85
  86         # run the loop of the instructions on the current test
  87         index = sim.pc.CIA.value//4
  88         while index < len(instructions):
  89             ins, code = instructions[index]
  90
  91             # extra new-line so it's easier to visually separate each
  92             # instruction in output
  93             log(f"\n0x{sim.pc.CIA.value:04X}: {ins % (1 << 32):08X} {code}",
  94                 kind=LogType.InstrInOuts)
  95
  96             log("sim instr: 0x{:X} pc=0x{:X}".format(ins & 0xffffffff,
  97                                                      sim.pc.CIA.value))
  98             log(index, code)
  99
 100             # set up simulated instruction (in simdec2)
 101             try:
 102                 yield from sim.setup_one()
 103             except KeyError:  # instruction not in imem: stop
 104                 break
 105             yield Settle()
 106
 107             # call simulated operation
 108             log("sim", code)
 109             yield from sim.execute_one()
 110             yield Settle()
 111             index = sim.pc.CIA.value//4
 112
 113             # get sim register and memory TestState, add to list
 114             state = yield from TestState("sim", sim, dut, code)
 115             sim_states.append(state)
 116
 117         log(f"final pc: 0x{sim.pc.CIA.value:X}", kind=LogType.InstrInOuts)
 118
 119         if self.dut.allow_overlap:
 120             # get last state, at end of run
 121             state = yield from TestState("sim", sim, dut, code)
 122             sim_states.append(state)
 123
 124         return sim_states
 125
 126
 127 class TestRunnerBase(FHDLTestCase):
 128     """TestRunnerBase:  Sets up and executes the running of tests
 129     contained in tst_data. run_hdl (if provided) is an HDLRunner
 130     object.  If not provided, hdl simulation is skipped.
 131
 132     ISACaller simulation can be skipped by setting run_sim=False.
 133
 134     When using an Expected state to test with, the expected state
 135     is passed in with tst_data.
 136     """
 137
 138     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 139                  svp64=True, run_hdl=None, run_sim=True,
 140                  allow_overlap=False, inorder=False, fp=False,
 141                  use_mmap_mem=False,
 142                  use_syscall_emu=False):
 143         super().__init__("run_all")
 144         self.test_data = tst_data
 145         self.microwatt_mmu = microwatt_mmu
 146         self.rom = rom
 147         self.svp64 = svp64
 148         self.allow_overlap = allow_overlap
 149         self.inorder = inorder
 150         self.run_hdl = run_hdl
 151         self.run_sim = run_sim
 152         self.fp = fp
 153         self.use_mmap_mem = use_mmap_mem
 154         self.use_syscall_emu = use_syscall_emu
 155
 156     def run_all(self):
 157         m = Module()
 158         comb = m.d.comb
 159         if self.microwatt_mmu:
 160             # do not wire these up to anything if wb_get is to be used
 161             if self.rom is not None:
 162                 ldst_ifacetype = 'mmu_cache_wb'
 163                 imem_ifacetype = 'mmu_cache_wb'
 164             else:
 165                 ldst_ifacetype = 'test_mmu_cache_wb'
 166                 imem_ifacetype = 'test_bare_wb'
 167         else:
 168             ldst_ifacetype = 'test_bare_wb'
 169             imem_ifacetype = 'test_bare_wb'
 170
 171         pspec = Mock(ldst_ifacetype=ldst_ifacetype,
 172                      imem_ifacetype=imem_ifacetype,
 173                      addr_wid=64,
 174                      mask_wid=8,
 175                      XLEN=64,
 176                      imem_reg_wid=64,
 177                      # wb_data_width=32,
 178                      use_pll=False,
 179                      nocore=False,
 180                      xics=False,
 181                      gpio=False,
 182                      regreduce=not self.allow_overlap,
 183                      core_domain="sync",  # no alternative domain
 184                      svp64=self.svp64,
 185                      allow_overlap=self.allow_overlap,
 186                      inorder=self.inorder,
 187                      mmu=self.microwatt_mmu,
 188                      reg_wid=64,
 189                      fp_en=self.fp)
 190
 191         ###### SETUP PHASE #######
 192         # Determine the simulations needed and add to state_list
 193         # for setup and running
 194         # The methods contained in the respective Runner classes are
 195         # called using this list when possible
 196
 197         # allow wb_get to run
 198         if self.rom is not None:
 199             wbget.stop = False
 200
 201         state_list = []
 202
 203         if self.run_hdl:
 204             hdlrun = self.run_hdl(self, m, pspec)
 205             state_list.append(hdlrun)
 206
 207         if self.run_sim:
 208             simrun = SimRunner(self, m, pspec,
 209                 use_mmap_mem=self.use_mmap_mem,
 210                 use_syscall_emu=self.use_syscall_emu)
 211             state_list.append(simrun)
 212
 213         # run core clock at same rate as test clock
 214         # XXX this has to stay here! TODO, work out why,
 215         # but Simulation-only fails without it
 216         intclk = ClockSignal("coresync")
 217         comb += intclk.eq(ClockSignal())
 218         dbgclk = ClockSignal("dbgsync")
 219         comb += dbgclk.eq(ClockSignal())
 220
 221         # nmigen Simulation - everything runs around this, so it
 222         # still has to be created.
 223         sim = Simulator(m)
 224         sim.add_clock(1e-6)
 225
 226         def process():
 227
 228             ###### PREPARATION PHASE AT START OF RUNNING #######
 229
 230             for runner in state_list:
 231                 yield from runner.setup_during_test()
 232
 233             # get each test, completely reset the core, and run it
 234
 235             for test in self.test_data:
 236                 with self.subTest(test.name, **test.subtest_args):
 237
 238                     ###### PREPARATION PHASE AT START OF TEST #######
 239
 240                     # HACK: if there is test memory and wb_get is in use,
 241                     # overwrite (reset) the wb_get memory dictionary with
 242                     # the test's memory contents (oh, and put the wb_get
 243                     # memory back in as well)
 244                     self.default_mem.clear()
 245                     if self.rom is not None:
 246                         self.default_mem.update(deepcopy(self.rom))
 247                     if test.mem is not None:
 248                         self.default_mem.update(deepcopy(test.mem))
 249
 250                     for runner in state_list:
 251                         yield from runner.prepare_for_test(test)
 252
 253                     log("running test: ", test.name, test.subtest_args,
 254                         kind=LogType.InstrInOuts)
 255                     program = test.program
 256
 257                     def format_regs(regs):
 258                         # type: (list[int]) -> str
 259                         out = []
 260                         for i, v in enumerate(regs):
 261                             values = ""
 262                             for sz in (32, 64):
 263                                 for signed in ("u", "i"):
 264                                     value = v % (1 << sz)
 265                                     if signed == "i" and \
 266                                             value & (1 << (sz - 1)) != 0:
 267                                         value -= 1 << sz
 268                                     values += f" {signed}{sz}:{value}"
 269                             out.append(f"r{i} = 0x{v:X} {values}")
 270                         return "\n".join(out)
 271                     log("regs:", format_regs(test.regs),
 272                         kind=LogType.InstrInOuts)
 273                     log("sprs", test.sprs, kind=LogType.InstrInOuts)
 274                     log("cr", test.cr, kind=LogType.InstrInOuts)
 275                     log("mem", test.mem)
 276                     log("msr", test.msr, kind=LogType.InstrInOuts)
 277
 278                     def format_assembly(assembly):
 279                         # type: (str) -> str
 280                         pc = 0
 281                         out = []
 282                         for line in assembly.splitlines():
 283                             out.append(f"pc=0x{pc:04X}: {line}")
 284                             if not line.startswith(".set ") and \
 285                                     line.partition('#')[0].strip() != "":
 286                                 pc += 4
 287                         return "\n".join(out)
 288                     log("assembly:\n" + format_assembly(program.assembly),
 289                         kind=LogType.InstrInOuts)
 290                     gen = list(program.generate_instructions())
 291                     insncode = program.assembly.splitlines()
 292                     instructions = list(zip(gen, insncode))
 293
 294                     ###### RUNNING OF EACH TEST #######
 295                     # StateRunner.step_test()
 296
 297                     # Run two tests (TODO, move these to functions)
 298                     # * first the Simulator, collate a batch of results
 299                     # * then the HDL, likewise
 300                     #   (actually, the other way round because running
 301                     #    Simulator somehow modifies the test state!)
 302                     # * finally, compare all the results
 303
 304                     # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 305
 306                     ##########
 307                     # 1. HDL
 308                     ##########
 309                     if self.run_hdl:
 310                         hdl_states = yield from hdlrun.run_test(instructions)
 311
 312                     ##########
 313                     # 2. Simulator
 314                     ##########
 315
 316                     if self.run_sim:
 317                         sim_states = yield from simrun.run_test(
 318                             instructions, gen,
 319                             insncode)
 320
 321                     ###### COMPARING THE TESTS #######
 322
 323                     ###############
 324                     # 3. Compare
 325                     ###############
 326
 327                     # TODO: here just grab one entry from list_of_sim_runners
 328                     # (doesn't matter which one, honestly)
 329                     # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 330
 331                     if self.run_sim:
 332                         last_sim = copy(sim_states[-1])
 333                     elif self.run_hdl:
 334                         last_sim = copy(hdl_states[-1])
 335                     else:
 336                         last_sim = None  # err what are you doing??
 337
 338                     if self.run_hdl:
 339                         log("hdl_states")
 340                         for state in hdl_states:
 341                             log(state)
 342
 343                     # FIXME: commented until SimState has a __repr__
 344                     # if self.run_sim:
 345                     #     log("sim_states")
 346                     #     for state in sim_states:
 347                     #         log(state)
 348
 349                     # compare the states
 350                     if self.run_hdl and self.run_sim:
 351                         # if allow_overlap is enabled, because allow_overlap
 352                         # can commit out-of-order, only compare the last ones
 353                         if self.allow_overlap:
 354                             log("allow_overlap: truncating %d %d "
 355                                 "states to last" % (len(sim_states),
 356                                                     len(hdl_states)))
 357                             sim_states = sim_states[-1:]
 358                             hdl_states = hdl_states[-1:]
 359                             sim_states[-1].dump_state_tofile()
 360                             log("allow_overlap: last hdl_state")
 361                             hdl_states[-1].dump_state_tofile()
 362                         for simstate, hdlstate in zip(sim_states, hdl_states):
 363                             simstate.compare(hdlstate)     # register check
 364                             simstate.compare_mem(hdlstate)  # memory check
 365
 366                     # if no expected, create /tmp/case_name.py with code
 367                     # setting expected state to last_sim
 368                     if test.expected is None:
 369                         last_sim.dump_state_tofile(test.name, test.test_file)
 370
 371                     # compare against expected results
 372                     if test.expected is not None:
 373                         # have to put these in manually
 374                         test.expected.to_test = test.expected
 375                         test.expected.dut = self
 376                         test.expected.state_type = "expected"
 377                         test.expected.code = 0
 378                         # do actual comparison, against last item
 379                         last_sim.compare(test.expected)
 380
 381                     # check number of instructions run (sanity)
 382                     if self.run_hdl and self.run_sim:
 383                         n_hdl = len(hdl_states)
 384                         n_sim = len(sim_states)
 385                         self.assertTrue(n_hdl == n_sim,
 386                                         "number of instructions %d %d "
 387                                         "run not the same" % (n_hdl, n_sim))
 388
 389                 ###### END OF A TEST #######
 390                 # StateRunner.end_test()
 391
 392                 for runner in state_list:
 393                     yield from runner.end_test()  # TODO, some arguments?
 394
 395             ###### END OF EVERYTHING (but none needs doing, still call fn) ####
 396             # StateRunner.cleanup()
 397
 398             for runner in state_list:
 399                 yield from runner.cleanup()  # TODO, some arguments?
 400
 401             # finally stop wb_get from going
 402             if self.rom is not None:
 403                 wbget.stop = True
 404
 405         styles = {
 406             'dec': {'base': 'dec'},
 407             'bin': {'base': 'bin'},
 408             'closed': {'closed': True}
 409         }
 410
 411         traces = [
 412             'clk',
 413             ('state machines', 'closed', [
 414                 'fetch_pc_i_valid', 'fetch_pc_o_ready',
 415                 'fetch_fsm_state',
 416                 'fetch_insn_o_valid', 'fetch_insn_i_ready',
 417                 'pred_insn_i_valid', 'pred_insn_o_ready',
 418                 'fetch_predicate_state',
 419                 'pred_mask_o_valid', 'pred_mask_i_ready',
 420                 'issue_fsm_state',
 421                 'exec_insn_i_valid', 'exec_insn_o_ready',
 422                 'exec_fsm_state',
 423                 'exec_pc_o_valid', 'exec_pc_i_ready',
 424                 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
 425                 'is_last', 'dec2.no_out_vec']),
 426             {'comment': 'fetch and decode'},
 427             (None, 'dec', [
 428                 'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'msr[63:0]',
 429                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
 430             'raw_insn_i[31:0]',
 431             'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
 432             ('svp64 decoding', 'closed', [
 433                 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
 434                 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
 435                 'dec2.sv_rm_dec.ptype_in',
 436                 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
 437                 'dstmask[63:0]', 'srcmask[63:0]',
 438                 'dregread[4:0]', 'dinvert',
 439                 'sregread[4:0]', 'sinvert',
 440                 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
 441                 'core.int.pred__ren']),
 442             ('register augmentation', 'dec', 'closed', [
 443                 {'comment': 'v3.0b registers'},
 444                 'dec2.dec_o.RT[4:0]',
 445                 'dec2.dec_a.RA[4:0]',
 446                 'dec2.dec_b.RB[4:0]',
 447                 ('Rdest', [
 448                     'dec2.o_svdec.reg_in[4:0]',
 449                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 450                     'dec2.o_svdec.reg_out[6:0]']),
 451                 ('Rsrc1', [
 452                     'dec2.in1_svdec.reg_in[4:0]',
 453                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 454                     'dec2.in1_svdec.reg_out[6:0]']),
 455                 ('Rsrc1', [
 456                     'dec2.in2_svdec.reg_in[4:0]',
 457                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 458                     'dec2.in2_svdec.reg_out[6:0]']),
 459                 {'comment': 'SVP64 registers'},
 460                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 461             ]),
 462             {'comment': 'svp64 context'},
 463             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 464             'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
 465             'core_core_dststep[6:0]',
 466             {'comment': 'issue and execute'},
 467             'core.core_core_insn_type',
 468             (None, 'dec', [
 469                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 470             'issue_i', 'busy_o',
 471             {'comment': 'dmi'},
 472             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 473             {'comment': 'instruction memory'},
 474             'imem.sram.rdport.memory(0)[63:0]',
 475             {'comment': 'registers'},
 476             # match with soc.regfile.regfiles.IntRegs port names
 477             'core.int.rp_src1.memory(0)[63:0]',
 478             'core.int.rp_src1.memory(1)[63:0]',
 479             'core.int.rp_src1.memory(2)[63:0]',
 480             'core.int.rp_src1.memory(3)[63:0]',
 481             'core.int.rp_src1.memory(4)[63:0]',
 482             'core.int.rp_src1.memory(5)[63:0]',
 483             'core.int.rp_src1.memory(6)[63:0]',
 484             'core.int.rp_src1.memory(7)[63:0]',
 485             'core.int.rp_src1.memory(9)[63:0]',
 486             'core.int.rp_src1.memory(10)[63:0]',
 487             'core.int.rp_src1.memory(13)[63:0]',
 488             # Exceptions: see list archive for description of the chain
 489             # http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-December/004220.html
 490             ('exceptions', 'closed', [
 491                 'exc_happened',
 492                 'pdecode2.exc_happened',
 493                 'core.exc_happened',
 494                 'core.fus.ldst0.exc_o_happened']),
 495         ]
 496
 497         # PortInterface module path varies depending on MMU option
 498         if self.microwatt_mmu:
 499             pi_module = 'core.ldst0'
 500         else:
 501             pi_module = 'core.fus.ldst0'
 502
 503         traces += [('ld/st port interface', {'submodule': pi_module}, [
 504             'oper_r__insn_type',
 505             'oper_r__msr[63:0]',
 506             'ldst_port0_is_ld_i',
 507             'ldst_port0_is_st_i',
 508             'ldst_port0_busy_o',
 509             'ldst_port0_addr_i[47:0]',
 510             'ldst_port0_addr_i_ok',
 511             'ldst_port0_addr_ok_o',
 512             'ldst_port0_exc_happened',
 513             'ldst_port0_st_data_i[63:0]',
 514             'ldst_port0_st_data_i_ok',
 515             'ldst_port0_ld_data_o[63:0]',
 516             'ldst_port0_ld_data_o_ok',
 517             'ldst_port0_msr_pr',
 518             'exc_o_happened',
 519             'cancel'
 520         ])]
 521
 522         if self.microwatt_mmu:
 523             traces += [
 524                 {'comment': 'microwatt_mmu'},
 525                 'core.fus.mmu0.alu_mmu0.illegal',
 526                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 527                 'core.fus.mmu0.alu_mmu0.mmu.state',
 528                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 529                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 530                 {'comment': 'wishbone_memory'},
 531                 'core.l0.pimem.bus__ack',
 532                 'core.l0.pimem.bus__adr[4:0]',
 533                 'core.l0.pimem.bus__bte',
 534                 'core.l0.pimem.bus__cti',
 535                 'core.l0.pimem.bus__cyc',
 536                 'core.l0.pimem.bus__dat_r[63:0]',
 537                 'core.l0.pimem.bus__dat_w[63:0]',
 538                 'core.l0.pimem.bus__dat_err',
 539                 'core.l0.pimem.bus__dat_sel[7:0]',
 540                 'core.l0.pimem.bus__dat_stb',
 541                 'core.l0.pimem.bus__dat_we',
 542             ]
 543
 544         gtkname = "issuer_simulator"
 545         if self.rom:
 546             gtkname += "_mmu"
 547
 548         write_gtkw("%s.gtkw" % gtkname,
 549                    "%s.vcd" % gtkname,
 550                    traces, styles, module='bench.top.issuer')
 551
 552         # add run of instructions
 553         sim.add_sync_process(process)
 554
 555         # ARGH oh whoops. TODO, core is not passed in!
 556         # urrr... work out a hacky-way to sort this (access run_hdl
 557         # core directly for now)
 558
 559         # optionally, if a wishbone-based ROM is passed in, run that as an
 560         # extra emulated process
 561         self.default_mem = {}
 562         if self.rom is not None:
 563             log("TestRunner with MMU ROM")
 564             log(pformat(self.rom))
 565             dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache
 566             icache = hdlrun.issuer.core.fus.fus["mmu0"].alu.icache
 567             self.default_mem = deepcopy(self.rom)
 568             sim.add_sync_process(wrap(wb_get(dcache.bus,
 569                                              self.default_mem, "DCACHE")))
 570             sim.add_sync_process(wrap(wb_get(icache.ibus,
 571                                              self.default_mem, "ICACHE")))
 572
 573         with sim.write_vcd("%s.vcd" % gtkname):
 574             sim.run()