1 """TestRunner class, part of the Test API
5 Copyright (C) 2020,2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 Copyright (C) 2021 Kyle Lehman <klehman9@comcast.net>
7 Copyright (C) 2021 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
8 Copyright (C) 2021 Tobias Platen <tplaten@posteo.de>
9 Copyright (C) 2021 Cesar Strauss <cestrauss@gmail.com>
13 * https://bugs.libre-soc.org/show_bug.cgi?id=363
14 * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
17 from nmigen
import Module
, ClockSignal
18 from copy
import copy
, deepcopy
19 from pprint
import pprint
21 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
22 # Also, check out the cxxsim nmigen branch, and latest yosys from git
23 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
25 from nmutil
.formaltest
import FHDLTestCase
26 from nmutil
.gtkw
import write_gtkw
27 from openpower
.decoder
.isa
.all
import ISA
28 from openpower
.endian
import bigendian
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
32 from soc
.config
.test
.test_loadstore
import TestMemPspec
33 from nmutil
.util
import wrap
34 from openpower
.test
.wb_get
import wb_get
35 import openpower
.test
.wb_get
as wbget
36 from openpower
.test
.state
import TestState
, StateRunner
, ExpectedState
39 class SimRunner(StateRunner
):
40 """SimRunner: Implements methods for the setup, preparation, and
41 running of tests using ISACaller simulation
43 def __init__(self
, dut
, m
, pspec
):
44 super().__init
__("sim", SimRunner
)
47 self
.mmu
= pspec
.mmu
== True
48 regreduce_en
= pspec
.regreduce_en
== True
49 self
.simdec2
= simdec2
= PowerDecode2(None, regreduce_en
=regreduce_en
)
50 m
.submodules
.simdec2
= simdec2
# pain in the neck
52 def prepare_for_test(self
, test
):
57 def run_test(self
, instructions
, gen
, insncode
):
58 """run_sim_state - runs an ISACaller simulation
61 dut
, test
, simdec2
= self
.dut
, self
.test
, self
.simdec2
64 # set up the Simulator (which must track TestIssuer exactly)
65 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
67 initial_insns
=gen
, respect_pc
=True,
70 initial_svstate
=test
.svstate
,
73 # run the loop of the instructions on the current test
74 index
= sim
.pc
.CIA
.value
//4
75 while index
< len(instructions
):
76 ins
, code
= instructions
[index
]
78 print("sim instr: 0x{:X}".format(ins
& 0xffffffff))
81 # set up simulated instruction (in simdec2)
83 yield from sim
.setup_one()
84 except KeyError: # instruction not in imem: stop
88 # call simulated operation
90 yield from sim
.execute_one()
92 index
= sim
.pc
.CIA
.value
//4
94 # get sim register and memory TestState, add to list
95 state
= yield from TestState("sim", sim
, dut
, code
)
96 sim_states
.append(state
)
98 if self
.dut
.allow_overlap
:
99 # get last state, at end of run
100 state
= yield from TestState("sim", sim
, dut
, code
)
101 sim_states
.append(state
)
106 class TestRunnerBase(FHDLTestCase
):
107 """TestRunnerBase: Sets up and executes the running of tests
108 contained in tst_data. run_hdl (if provided) is an HDLRunner
109 object. If not provided, hdl simulation is skipped.
111 ISACaller simulation can be skipped by setting run_sim=False.
113 When using an Expected state to test with, the expected state
114 is passed in with tst_data.
116 def __init__(self
, tst_data
, microwatt_mmu
=False, rom
=None,
117 svp64
=True, run_hdl
=None, run_sim
=True,
118 allow_overlap
=False, inorder
=False):
119 super().__init
__("run_all")
120 self
.test_data
= tst_data
121 self
.microwatt_mmu
= microwatt_mmu
124 self
.allow_overlap
= allow_overlap
125 self
.inorder
= inorder
126 self
.run_hdl
= run_hdl
127 self
.run_sim
= run_sim
132 if self
.microwatt_mmu
:
133 # do not wire these up to anything if wb_get is to be used
134 if self
.rom
is not None:
135 ldst_ifacetype
= 'mmu_cache_wb'
136 imem_ifacetype
= 'mmu_cache_wb'
138 ldst_ifacetype
= 'test_mmu_cache_wb'
139 imem_ifacetype
= 'test_bare_wb'
141 ldst_ifacetype
= 'test_bare_wb'
142 imem_ifacetype
= 'test_bare_wb'
144 pspec
= TestMemPspec(ldst_ifacetype
=ldst_ifacetype
,
145 imem_ifacetype
=imem_ifacetype
,
154 regreduce
=not self
.allow_overlap
,
155 core_domain
="sync", # no alternative domain
157 allow_overlap
=self
.allow_overlap
,
158 inorder
=self
.inorder
,
159 mmu
=self
.microwatt_mmu
,
162 ###### SETUP PHASE #######
163 # Determine the simulations needed and add to state_list
164 # for setup and running
165 # The methods contained in the respective Runner classes are
166 # called using this list when possible
168 # allow wb_get to run
169 if self
.rom
is not None:
175 hdlrun
= self
.run_hdl(self
, m
, pspec
)
176 state_list
.append(hdlrun
)
179 simrun
= SimRunner(self
, m
, pspec
)
180 state_list
.append(simrun
)
182 # run core clock at same rate as test clock
183 # XXX this has to stay here! TODO, work out why,
184 # but Simulation-only fails without it
185 intclk
= ClockSignal("coresync")
186 comb
+= intclk
.eq(ClockSignal())
187 dbgclk
= ClockSignal("dbgsync")
188 comb
+= dbgclk
.eq(ClockSignal())
190 # nmigen Simulation - everything runs around this, so it
191 # still has to be created.
197 ###### PREPARATION PHASE AT START OF RUNNING #######
199 for runner
in state_list
:
200 yield from runner
.setup_during_test()
202 # get each test, completely reset the core, and run it
204 for test
in self
.test_data
:
206 with self
.subTest(test
.name
):
208 ###### PREPARATION PHASE AT START OF TEST #######
210 # HACK: if there is test memory and wb_get is in use,
211 # overwrite (reset) the wb_get memory dictionary with
212 # the test's memory contents (oh, and put the wb_get
213 # memory back in as well)
214 self
.default_mem
.clear()
215 if self
.rom
is not None:
216 self
.default_mem
.update(deepcopy(self
.rom
))
217 if test
.mem
is not None:
218 self
.default_mem
.update(deepcopy(test
.mem
))
220 for runner
in state_list
:
221 yield from runner
.prepare_for_test(test
)
224 program
= test
.program
225 print("regs", test
.regs
)
226 print("sprs", test
.sprs
)
228 print("mem", test
.mem
)
229 print("msr", test
.msr
)
230 print("assem", program
.assembly
)
231 gen
= list(program
.generate_instructions())
232 insncode
= program
.assembly
.splitlines()
233 instructions
= list(zip(gen
, insncode
))
235 ###### RUNNING OF EACH TEST #######
236 # StateRunner.step_test()
238 # Run two tests (TODO, move these to functions)
239 # * first the Simulator, collate a batch of results
240 # * then the HDL, likewise
241 # (actually, the other way round because running
242 # Simulator somehow modifies the test state!)
243 # * finally, compare all the results
245 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
251 hdl_states
= yield from hdlrun
.run_test(instructions
)
258 sim_states
= yield from simrun
.run_test(
262 ###### COMPARING THE TESTS #######
268 # TODO: here just grab one entry from list_of_sim_runners
269 # (doesn't matter which one, honestly)
270 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
273 last_sim
= copy(sim_states
[-1])
275 last_sim
= copy(hdl_states
[-1])
277 last_sim
= None # err what are you doing??
281 for state
in hdl_states
:
286 for state
in sim_states
:
290 if self
.run_hdl
and self
.run_sim
:
291 # if allow_overlap is enabled, because allow_overlap
292 # can commit out-of-order, only compare the last ones
293 if self
.allow_overlap
:
294 print ("allow_overlap: truncating %d %d "
295 "states to last" % (len(sim_states
),
297 sim_states
= sim_states
[-1:]
298 hdl_states
= hdl_states
[-1:]
299 sim_states
[-1].dump_state_tofile()
300 print ("allow_overlap: last hdl_state")
301 hdl_states
[-1].dump_state_tofile()
302 for simstate
, hdlstate
in zip(sim_states
, hdl_states
):
303 simstate
.compare(hdlstate
) # register check
304 simstate
.compare_mem(hdlstate
) # memory check
306 # if no expected, create /tmp/case_name.py with code
307 # setting expected state to last_sim
308 if test
.expected
is None:
309 last_sim
.dump_state_tofile(test
.name
, test
.test_file
)
311 # compare against expected results
312 if test
.expected
is not None:
313 # have to put these in manually
314 test
.expected
.to_test
= test
.expected
315 test
.expected
.dut
= self
316 test
.expected
.state_type
= "expected"
317 test
.expected
.code
= 0
318 # do actual comparison, against last item
319 last_sim
.compare(test
.expected
)
321 # check number of instructions run (sanity)
322 if self
.run_hdl
and self
.run_sim
:
323 n_hdl
= len(hdl_states
)
324 n_sim
= len(sim_states
)
325 self
.assertTrue(n_hdl
== n_sim
,
326 "number of instructions %d %d "
327 "run not the same" % (n_hdl
, n_sim
))
329 ###### END OF A TEST #######
330 # StateRunner.end_test()
332 for runner
in state_list
:
333 yield from runner
.end_test() # TODO, some arguments?
335 ###### END OF EVERYTHING (but none needs doing, still call fn) ####
336 # StateRunner.cleanup()
338 for runner
in state_list
:
339 yield from runner
.cleanup() # TODO, some arguments?
341 # finally stop wb_get from going
342 if self
.rom
is not None:
346 'dec': {'base': 'dec'},
347 'bin': {'base': 'bin'},
348 'closed': {'closed': True}
353 ('state machines', 'closed', [
354 'fetch_pc_i_valid', 'fetch_pc_o_ready',
356 'fetch_insn_o_valid', 'fetch_insn_i_ready',
357 'pred_insn_i_valid', 'pred_insn_o_ready',
358 'fetch_predicate_state',
359 'pred_mask_o_valid', 'pred_mask_i_ready',
361 'exec_insn_i_valid', 'exec_insn_o_ready',
363 'exec_pc_o_valid', 'exec_pc_i_ready',
364 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
365 'is_last', 'dec2.no_out_vec']),
366 {'comment': 'fetch and decode'},
368 'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'msr[63:0]',
369 'cur_pc[63:0]', 'core_core_cia[63:0]']),
371 'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
372 ('svp64 decoding', 'closed', [
373 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
374 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
375 'dec2.sv_rm_dec.ptype_in',
376 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
377 'dstmask[63:0]', 'srcmask[63:0]',
378 'dregread[4:0]', 'dinvert',
379 'sregread[4:0]', 'sinvert',
380 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
381 'core.int.pred__ren']),
382 ('register augmentation', 'dec', 'closed', [
383 {'comment': 'v3.0b registers'},
384 'dec2.dec_o.RT[4:0]',
385 'dec2.dec_a.RA[4:0]',
386 'dec2.dec_b.RB[4:0]',
388 'dec2.o_svdec.reg_in[4:0]',
389 ('dec2.o_svdec.spec[2:0]', 'bin'),
390 'dec2.o_svdec.reg_out[6:0]']),
392 'dec2.in1_svdec.reg_in[4:0]',
393 ('dec2.in1_svdec.spec[2:0]', 'bin'),
394 'dec2.in1_svdec.reg_out[6:0]']),
396 'dec2.in2_svdec.reg_in[4:0]',
397 ('dec2.in2_svdec.spec[2:0]', 'bin'),
398 'dec2.in2_svdec.reg_out[6:0]']),
399 {'comment': 'SVP64 registers'},
400 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
402 {'comment': 'svp64 context'},
403 'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
404 'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
405 'core_core_dststep[6:0]',
406 {'comment': 'issue and execute'},
407 'core.core_core_insn_type',
409 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
412 'dbg.dmi_req_i', 'dbg.dmi_ack_o',
413 {'comment': 'instruction memory'},
414 'imem.sram.rdport.memory(0)[63:0]',
415 {'comment': 'registers'},
416 # match with soc.regfile.regfiles.IntRegs port names
417 'core.int.rp_src1.memory(0)[63:0]',
418 'core.int.rp_src1.memory(1)[63:0]',
419 'core.int.rp_src1.memory(2)[63:0]',
420 'core.int.rp_src1.memory(3)[63:0]',
421 'core.int.rp_src1.memory(4)[63:0]',
422 'core.int.rp_src1.memory(5)[63:0]',
423 'core.int.rp_src1.memory(6)[63:0]',
424 'core.int.rp_src1.memory(7)[63:0]',
425 'core.int.rp_src1.memory(9)[63:0]',
426 'core.int.rp_src1.memory(10)[63:0]',
427 'core.int.rp_src1.memory(13)[63:0]',
428 # Exceptions: see list archive for description of the chain
429 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-December/004220.html
430 ('exceptions', 'closed', [
432 'pdecode2.exc_happened',
434 'core.fus.ldst0.exc_o_happened']),
437 # PortInterface module path varies depending on MMU option
438 if self
.microwatt_mmu
:
439 pi_module
= 'core.ldst0'
441 pi_module
= 'core.fus.ldst0'
443 traces
+= [('ld/st port interface', {'submodule': pi_module
}, [
446 'ldst_port0_is_ld_i',
447 'ldst_port0_is_st_i',
449 'ldst_port0_addr_i[47:0]',
450 'ldst_port0_addr_i_ok',
451 'ldst_port0_addr_ok_o',
452 'ldst_port0_exc_happened',
453 'ldst_port0_st_data_i[63:0]',
454 'ldst_port0_st_data_i_ok',
455 'ldst_port0_ld_data_o[63:0]',
456 'ldst_port0_ld_data_o_ok',
462 if self
.microwatt_mmu
:
464 {'comment': 'microwatt_mmu'},
465 'core.fus.mmu0.alu_mmu0.illegal',
466 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
467 'core.fus.mmu0.alu_mmu0.mmu.state',
468 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
469 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
470 {'comment': 'wishbone_memory'},
471 'core.l0.pimem.bus__ack',
472 'core.l0.pimem.bus__adr[4:0]',
473 'core.l0.pimem.bus__bte',
474 'core.l0.pimem.bus__cti',
475 'core.l0.pimem.bus__cyc',
476 'core.l0.pimem.bus__dat_r[63:0]',
477 'core.l0.pimem.bus__dat_w[63:0]',
478 'core.l0.pimem.bus__dat_err',
479 'core.l0.pimem.bus__dat_sel[7:0]',
480 'core.l0.pimem.bus__dat_stb',
481 'core.l0.pimem.bus__dat_we',
484 gtkname
= "issuer_simulator"
488 write_gtkw("%s.gtkw" % gtkname
,
490 traces
, styles
, module
='top.issuer')
492 # add run of instructions
493 sim
.add_sync_process(process
)
495 # ARGH oh whoops. TODO, core is not passed in!
496 # urrr... work out a hacky-way to sort this (access run_hdl
497 # core directly for now)
499 # optionally, if a wishbone-based ROM is passed in, run that as an
500 # extra emulated process
501 self
.default_mem
= {}
502 if self
.rom
is not None:
503 print ("TestRunner with MMU ROM")
505 dcache
= hdlrun
.issuer
.core
.fus
.fus
["mmu0"].alu
.dcache
506 icache
= hdlrun
.issuer
.core
.fus
.fus
["mmu0"].alu
.icache
507 self
.default_mem
= deepcopy(self
.rom
)
508 sim
.add_sync_process(wrap(wb_get(dcache
.bus
,
509 self
.default_mem
, "DCACHE")))
510 sim
.add_sync_process(wrap(wb_get(icache
.ibus
,
511 self
.default_mem
, "ICACHE")))
513 with sim
.write_vcd("%s.vcd" % gtkname
):