src/openpower/test/runner.py

   1 """TestRunner class, part of the Test API
   2
   3 SPDX-License: LGPLv2+
   4
   5 Copyright (C) 2020,2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6 Copyright (C) 2021 Kyle Lehman <klehman9@comcast.net>
   7 Copyright (C) 2021 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
   8 Copyright (C) 2021 Tobias Platen <tplaten@posteo.de>
   9 Copyright (C) 2021 Cesar Strauss <cestrauss@gmail.com>
  10
  11 related bugs:
  12
  13  * https://bugs.libre-soc.org/show_bug.cgi?id=363
  14  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
  15 """
  16
  17 from nmigen import Module, ClockSignal
  18 from copy import copy
  19 from pprint import pprint
  20
  21 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  22 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  23 from nmutil.sim_tmp_alternative import Simulator, Settle
  24
  25 from nmutil.formaltest import FHDLTestCase
  26 from nmutil.gtkw import write_gtkw
  27 from openpower.decoder.isa.all import ISA
  28 from openpower.endian import bigendian
  29
  30 from openpower.decoder.power_decoder2 import PowerDecode2
  31
  32 from soc.config.test.test_loadstore import TestMemPspec
  33 from nmutil.util import wrap
  34 from openpower.test.wb_get import wb_get
  35 import openpower.test.wb_get as wbget
  36 from openpower.test.state import TestState, StateRunner, ExpectedState
  37
  38
  39 class SimRunner(StateRunner):
  40     """SimRunner:  Implements methods for the setup, preparation, and
  41     running of tests using ISACaller simulation
  42     """
  43     def __init__(self, dut, m, pspec):
  44         super().__init__("sim", SimRunner)
  45         self.dut = dut
  46
  47         self.mmu = pspec.mmu == True
  48         regreduce_en = pspec.regreduce_en == True
  49         self.simdec2 = simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
  50         m.submodules.simdec2 = simdec2  # pain in the neck
  51
  52     def prepare_for_test(self, test):
  53         self.test = test
  54         if False:
  55             yield
  56
  57     def run_test(self, instructions, gen, insncode):
  58         """run_sim_state - runs an ISACaller simulation
  59         """
  60
  61         dut, test, simdec2 = self.dut, self.test, self.simdec2
  62         sim_states = []
  63
  64         # set up the Simulator (which must track TestIssuer exactly)
  65         sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
  66                   test.msr,
  67                   initial_insns=gen, respect_pc=True,
  68                   disassembly=insncode,
  69                   bigendian=bigendian,
  70                   initial_svstate=test.svstate,
  71                   mmu=self.mmu)
  72
  73         # run the loop of the instructions on the current test
  74         index = sim.pc.CIA.value//4
  75         while index < len(instructions):
  76             ins, code = instructions[index]
  77
  78             print("sim instr: 0x{:X}".format(ins & 0xffffffff))
  79             print(index, code)
  80
  81             # set up simulated instruction (in simdec2)
  82             try:
  83                 yield from sim.setup_one()
  84             except KeyError:  # instruction not in imem: stop
  85                 break
  86             yield Settle()
  87
  88             # call simulated operation
  89             print("sim", code)
  90             yield from sim.execute_one()
  91             yield Settle()
  92             index = sim.pc.CIA.value//4
  93
  94             # get sim register and memory TestState, add to list
  95             state = yield from TestState("sim", sim, dut, code)
  96             sim_states.append(state)
  97
  98         if self.dut.allow_overlap:
  99             # get last state, at end of run
 100             state = yield from TestState("sim", sim, dut, code)
 101             sim_states.append(state)
 102
 103         return sim_states
 104
 105
 106 class TestRunnerBase(FHDLTestCase):
 107     """TestRunnerBase:  Sets up and executes the running of tests
 108     contained in tst_data. run_hdl (if provided) is an HDLRunner
 109     object.  If not provided, hdl simulation is skipped.
 110
 111     ISACaller simulation can be skipped by setting run_sim=False.
 112
 113     When using an Expected state to test with, the expected state
 114     is passed in with tst_data.
 115     """
 116     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 117                         svp64=True, run_hdl=None, run_sim=True,
 118                         allow_overlap=False):
 119         super().__init__("run_all")
 120         self.test_data = tst_data
 121         self.microwatt_mmu = microwatt_mmu
 122         self.rom = rom
 123         self.svp64 = svp64
 124         self.allow_overlap = allow_overlap
 125         self.run_hdl = run_hdl
 126         self.run_sim = run_sim
 127
 128     def run_all(self):
 129         m = Module()
 130         comb = m.d.comb
 131         if self.microwatt_mmu:
 132             # do not wire these up to anything if wb_get is to be used
 133             if self.rom is not None:
 134                 ldst_ifacetype = 'mmu_cache_wb'
 135                 imem_ifacetype = 'mmu_cache_wb'
 136             else:
 137                 ldst_ifacetype = 'test_mmu_cache_wb'
 138                 imem_ifacetype = 'test_bare_wb'
 139         else:
 140             ldst_ifacetype = 'test_bare_wb'
 141             imem_ifacetype = 'test_bare_wb'
 142
 143         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
 144                              imem_ifacetype=imem_ifacetype,
 145                              addr_wid=48,
 146                              mask_wid=8,
 147                              imem_reg_wid=64,
 148                              # wb_data_width=32,
 149                              use_pll=False,
 150                              nocore=False,
 151                              xics=False,
 152                              gpio=False,
 153                              regreduce=not self.allow_overlap,
 154                              core_domain="sync", # no alternative domain
 155                              svp64=self.svp64,
 156                              allow_overlap=self.allow_overlap,
 157                              mmu=self.microwatt_mmu,
 158                              reg_wid=64)
 159
 160         ###### SETUP PHASE #######
 161         # Determine the simulations needed and add to state_list
 162         # for setup and running
 163         # The methods contained in the respective Runner classes are
 164         # called using this list when possible
 165
 166         # allow wb_get to run
 167         if self.rom is not None:
 168             wbget.stop = False
 169
 170         state_list = []
 171
 172         if self.run_hdl:
 173             hdlrun = self.run_hdl(self, m, pspec)
 174             state_list.append(hdlrun)
 175
 176         if self.run_sim:
 177             simrun = SimRunner(self, m, pspec)
 178             state_list.append(simrun)
 179
 180         # run core clock at same rate as test clock
 181         # XXX this has to stay here! TODO, work out why,
 182         # but Simulation-only fails without it
 183         intclk = ClockSignal("coresync")
 184         comb += intclk.eq(ClockSignal())
 185         dbgclk = ClockSignal("dbgsync")
 186         comb += dbgclk.eq(ClockSignal())
 187
 188         # nmigen Simulation - everything runs around this, so it
 189         # still has to be created.
 190         sim = Simulator(m)
 191         sim.add_clock(1e-6)
 192
 193         def process():
 194
 195             ###### PREPARATION PHASE AT START OF RUNNING #######
 196
 197             for runner in state_list:
 198                 yield from runner.setup_during_test()
 199
 200             # get each test, completely reset the core, and run it
 201
 202             for test in self.test_data:
 203
 204                 with self.subTest(test.name):
 205
 206                     ###### PREPARATION PHASE AT START OF TEST #######
 207
 208                     for runner in state_list:
 209                         yield from runner.prepare_for_test(test)
 210
 211                     print(test.name)
 212                     program = test.program
 213                     print("regs", test.regs)
 214                     print("sprs", test.sprs)
 215                     print("cr", test.cr)
 216                     print("mem", test.mem)
 217                     print("msr", test.msr)
 218                     print("assem", program.assembly)
 219                     gen = list(program.generate_instructions())
 220                     insncode = program.assembly.splitlines()
 221                     instructions = list(zip(gen, insncode))
 222
 223                     ###### RUNNING OF EACH TEST #######
 224                     # StateRunner.step_test()
 225
 226                     # Run two tests (TODO, move these to functions)
 227                     # * first the Simulator, collate a batch of results
 228                     # * then the HDL, likewise
 229                     #   (actually, the other way round because running
 230                     #    Simulator somehow modifies the test state!)
 231                     # * finally, compare all the results
 232
 233                     # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 234
 235                     ##########
 236                     # 1. HDL
 237                     ##########
 238                     if self.run_hdl:
 239                         hdl_states = yield from hdlrun.run_test(instructions)
 240
 241                     ##########
 242                     # 2. Simulator
 243                     ##########
 244
 245                     if self.run_sim:
 246                         sim_states = yield from simrun.run_test(
 247                                                           instructions, gen,
 248                                                           insncode)
 249
 250                     ###### COMPARING THE TESTS #######
 251
 252                     ###############
 253                     # 3. Compare
 254                     ###############
 255
 256                     # TODO: here just grab one entry from list_of_sim_runners
 257                     # (doesn't matter which one, honestly)
 258                     # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 259
 260                     if self.run_sim:
 261                         last_sim = copy(sim_states[-1])
 262                     elif self.run_hdl:
 263                         last_sim = copy(hdl_states[-1])
 264                     else:
 265                         last_sim = None # err what are you doing??
 266
 267                     if self.run_hdl:
 268                         print ("hdl_states")
 269                         for state in hdl_states:
 270                             print (state)
 271
 272                     if self.run_sim:
 273                         print ("sim_states")
 274                         for state in sim_states:
 275                             print (state)
 276
 277                     # compare the states
 278                     if self.run_hdl and self.run_sim:
 279                         # if allow_overlap is enabled, because allow_overlap
 280                         # can commit out-of-order, only compare the last ones
 281                         if self.allow_overlap:
 282                             print ("allow_overlap: truncating %d %d "
 283                                     "states to last" % (len(sim_states),
 284                                                         len(hdl_states)))
 285                             sim_states = sim_states[-1:]
 286                             hdl_states = hdl_states[-1:]
 287                             sim_states[-1].dump_state_tofile()
 288                             print ("allow_overlap: last hdl_state")
 289                             hdl_states[-1].dump_state_tofile()
 290                         for simstate, hdlstate in zip(sim_states, hdl_states):
 291                             simstate.compare(hdlstate)     # register check
 292                             simstate.compare_mem(hdlstate) # memory check
 293
 294                     # if no expected, create /tmp/case_name.py with code
 295                     # setting expected state to last_sim
 296                     if test.expected is None:
 297                         last_sim.dump_state_tofile(test.name, test.test_file)
 298
 299                     # compare against expected results
 300                     if test.expected is not None:
 301                         # have to put these in manually
 302                         test.expected.to_test = test.expected
 303                         test.expected.dut = self
 304                         test.expected.state_type = "expected"
 305                         test.expected.code = 0
 306                         # do actual comparison, against last item
 307                         last_sim.compare(test.expected)
 308
 309                     # check number of instructions run (sanity)
 310                     if self.run_hdl and self.run_sim:
 311                         n_hdl = len(hdl_states)
 312                         n_sim = len(sim_states)
 313                         self.assertTrue(n_hdl == n_sim,
 314                                     "number of instructions %d %d "
 315                                     "run not the same" % (n_hdl, n_sim))
 316
 317                 ###### END OF A TEST #######
 318                 # StateRunner.end_test()
 319
 320                 for runner in state_list:
 321                     yield from runner.end_test() # TODO, some arguments?
 322
 323             ###### END OF EVERYTHING (but none needs doing, still call fn) ####
 324             # StateRunner.cleanup()
 325
 326             for runner in state_list:
 327                 yield from runner.cleanup() # TODO, some arguments?
 328
 329             # finally stop wb_get from going
 330             if self.rom is not None:
 331                 wbget.stop = True
 332
 333         styles = {
 334             'dec': {'base': 'dec'},
 335             'bin': {'base': 'bin'},
 336             'closed': {'closed': True}
 337         }
 338
 339         traces = [
 340             'clk',
 341             ('state machines', 'closed', [
 342                 'fetch_pc_i_valid', 'fetch_pc_o_ready',
 343                 'fetch_fsm_state',
 344                 'fetch_insn_o_valid', 'fetch_insn_i_ready',
 345                 'pred_insn_i_valid', 'pred_insn_o_ready',
 346                 'fetch_predicate_state',
 347                 'pred_mask_o_valid', 'pred_mask_i_ready',
 348                 'issue_fsm_state',
 349                 'exec_insn_i_valid', 'exec_insn_o_ready',
 350                 'exec_fsm_state',
 351                 'exec_pc_o_valid', 'exec_pc_i_ready',
 352                 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
 353                 'is_last', 'dec2.no_out_vec']),
 354             {'comment': 'fetch and decode'},
 355             (None, 'dec', [
 356                 'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'msr[63:0]',
 357                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
 358             'raw_insn_i[31:0]',
 359             'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
 360             ('svp64 decoding', 'closed', [
 361                 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
 362                 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
 363                 'dec2.sv_rm_dec.ptype_in',
 364                 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
 365                 'dstmask[63:0]', 'srcmask[63:0]',
 366                 'dregread[4:0]', 'dinvert',
 367                 'sregread[4:0]', 'sinvert',
 368                 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
 369                 'core.int.pred__ren']),
 370             ('register augmentation', 'dec', 'closed', [
 371                 {'comment': 'v3.0b registers'},
 372                 'dec2.dec_o.RT[4:0]',
 373                 'dec2.dec_a.RA[4:0]',
 374                 'dec2.dec_b.RB[4:0]',
 375                 ('Rdest', [
 376                     'dec2.o_svdec.reg_in[4:0]',
 377                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 378                     'dec2.o_svdec.reg_out[6:0]']),
 379                 ('Rsrc1', [
 380                     'dec2.in1_svdec.reg_in[4:0]',
 381                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 382                     'dec2.in1_svdec.reg_out[6:0]']),
 383                 ('Rsrc1', [
 384                     'dec2.in2_svdec.reg_in[4:0]',
 385                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 386                     'dec2.in2_svdec.reg_out[6:0]']),
 387                 {'comment': 'SVP64 registers'},
 388                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 389             ]),
 390             {'comment': 'svp64 context'},
 391             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 392             'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
 393             'core_core_dststep[6:0]',
 394             {'comment': 'issue and execute'},
 395             'core.core_core_insn_type',
 396             (None, 'dec', [
 397                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 398             'issue_i', 'busy_o',
 399             {'comment': 'dmi'},
 400             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 401             {'comment': 'instruction memory'},
 402             'imem.sram.rdport.memory(0)[63:0]',
 403             {'comment': 'registers'},
 404             # match with soc.regfile.regfiles.IntRegs port names
 405             'core.int.rp_src1.memory(0)[63:0]',
 406             'core.int.rp_src1.memory(1)[63:0]',
 407             'core.int.rp_src1.memory(2)[63:0]',
 408             'core.int.rp_src1.memory(3)[63:0]',
 409             'core.int.rp_src1.memory(4)[63:0]',
 410             'core.int.rp_src1.memory(5)[63:0]',
 411             'core.int.rp_src1.memory(6)[63:0]',
 412             'core.int.rp_src1.memory(7)[63:0]',
 413             'core.int.rp_src1.memory(9)[63:0]',
 414             'core.int.rp_src1.memory(10)[63:0]',
 415             'core.int.rp_src1.memory(13)[63:0]',
 416             # Exceptions: see list archive for description of the chain
 417             # http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-December/004220.html
 418             ('exceptions', 'closed', [
 419                 'exc_happened',
 420                 'pdecode2.exc_happened',
 421                 'core.exc_happened',
 422                 'core.fus.ldst0.exc_o_happened']),
 423         ]
 424
 425         # PortInterface module path varies depending on MMU option
 426         if self.microwatt_mmu:
 427             pi_module = 'core.ldst0'
 428         else:
 429             pi_module = 'core.fus.ldst0'
 430
 431         traces += [('ld/st port interface', {'submodule': pi_module}, [
 432             'oper_r__insn_type',
 433             'oper_r__msr[63:0]',
 434             'ldst_port0_is_ld_i',
 435             'ldst_port0_is_st_i',
 436             'ldst_port0_busy_o',
 437             'ldst_port0_addr_i[47:0]',
 438             'ldst_port0_addr_i_ok',
 439             'ldst_port0_addr_ok_o',
 440             'ldst_port0_exc_happened',
 441             'ldst_port0_st_data_i[63:0]',
 442             'ldst_port0_st_data_i_ok',
 443             'ldst_port0_ld_data_o[63:0]',
 444             'ldst_port0_ld_data_o_ok',
 445             'ldst_port0_msr_pr',
 446             'exc_o_happened',
 447             'cancel'
 448         ])]
 449
 450         if self.microwatt_mmu:
 451             traces += [
 452                 {'comment': 'microwatt_mmu'},
 453                 'core.fus.mmu0.alu_mmu0.illegal',
 454                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 455                 'core.fus.mmu0.alu_mmu0.mmu.state',
 456                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 457                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 458                 {'comment': 'wishbone_memory'},
 459                 'core.l0.pimem.bus__ack',
 460                 'core.l0.pimem.bus__adr[4:0]',
 461                 'core.l0.pimem.bus__bte',
 462                 'core.l0.pimem.bus__cti',
 463                 'core.l0.pimem.bus__cyc',
 464                 'core.l0.pimem.bus__dat_r[63:0]',
 465                 'core.l0.pimem.bus__dat_w[63:0]',
 466                 'core.l0.pimem.bus__dat_err',
 467                 'core.l0.pimem.bus__dat_sel[7:0]',
 468                 'core.l0.pimem.bus__dat_stb',
 469                 'core.l0.pimem.bus__dat_we',
 470             ]
 471
 472         write_gtkw("issuer_simulator.gtkw",
 473                    "issuer_simulator.vcd",
 474                    traces, styles, module='top.issuer')
 475
 476         # add run of instructions
 477         sim.add_sync_process(process)
 478
 479         # ARGH oh whoops. TODO, core is not passed in!
 480         # urrr... work out a hacky-way to sort this (access run_hdl
 481         # core directly for now)
 482
 483         # optionally, if a wishbone-based ROM is passed in, run that as an
 484         # extra emulated process
 485         if self.rom is not None:
 486             print ("TestRunner with MMU ROM")
 487             pprint (self.rom)
 488             dcache = hdlrun.issuer.core.fus.fus["mmu0"].alu.dcache
 489             icache = hdlrun.issuer.core.fus.fus["mmu0"].alu.icache
 490             default_mem = self.rom
 491             sim.add_sync_process(wrap(wb_get(dcache.bus,
 492                                              default_mem, "DCACHE")))
 493             sim.add_sync_process(wrap(wb_get(icache.ibus,
 494                                              default_mem, "ICACHE")))
 495
 496         with sim.write_vcd("issuer_simulator.vcd"):
 497             sim.run()