take deepcopy of regs passed in to avoid accidental modification
[openpower-isa.git] / src / openpower / test / spr / spr_cases.py
1 from openpower.simulator.program import Program
2 from openpower.decoder.isa.all import ISA
3 from openpower.endian import bigendian
4 from openpower.consts import MSR
5
6
7 from openpower.test.common import TestAccumulatorBase, skip_case
8 import random
9
10
11 class SPRTestCase(TestAccumulatorBase):
12
13 def case_1_mfspr(self):
14 lst = ["mfspr 1, 26", # SRR0
15 "mfspr 2, 27", # SRR1
16 "mfspr 3, 8", # LR
17 "mfspr 4, 1", ] # XER
18 initial_regs = [0] * 32
19 initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
20 'XER': 0xe00c0000}
21 self.add_case(Program(lst, bigendian),
22 initial_regs, initial_sprs)
23
24 def case_1_mtspr(self):
25 lst = ["mtspr 26, 1", # SRR0
26 "mtspr 27, 2", # SRR1
27 "mtspr 1, 3", # XER
28 "mtspr 9, 4", ] # CTR
29 initial_regs = [0] * 32
30 initial_regs[1] = 0x129518230011feed
31 initial_regs[2] = 0x123518230011feed
32 initial_regs[3] = 0xe00c0000
33 initial_regs[4] = 0x1010101010101010
34 initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
35 'XER': 0x0}
36 self.add_case(Program(lst, bigendian),
37 initial_regs, initial_sprs)
38
39 def case_2_mtspr_mfspr(self):
40 lst = ["mtspr 26, 1", # SRR0
41 "mtspr 27, 2", # SRR1
42 "mtspr 1, 3", # XER
43 "mtspr 9, 4", # CTR
44 "mfspr 2, 26", # SRR0
45 "mfspr 3, 27", # and into reg 2
46 "mfspr 4, 1", # XER
47 "mfspr 5, 9", ] # CTR
48 initial_regs = [0] * 32
49 initial_regs[1] = 0x129518230011feed
50 initial_regs[2] = 0x123518230011feed
51 initial_regs[3] = 0xe00c0000
52 initial_regs[4] = 0x1010101010101010
53 initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
54 'XER': 0x0}
55 self.add_case(Program(lst, bigendian),
56 initial_regs, initial_sprs)
57
58 # TODO XXX whoops...
59 @skip_case("spr does not have TRAP in it. has to be done another way")
60 def case_3_mtspr_priv(self):
61 lst = ["mtspr 26, 1", # SRR0
62 "mtspr 27, 2", # SRR1
63 "mtspr 1, 3", # XER
64 "mtspr 9, 4", ] # CTR
65 initial_regs = [0] * 32
66 initial_regs[1] = 0x129518230011feed
67 initial_regs[2] = 0x123518230011feed
68 initial_regs[3] = 0xe00c0000
69 initial_regs[4] = 0x1010101010101010
70 initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
71 'XER': 0x0}
72 msr = 1 << MSR.PR
73 self.add_case(Program(lst, bigendian),
74 initial_regs, initial_sprs, initial_msr=msr)
75
76 def case_4_mfspr_slow(self):
77 lst = ["mfspr 1, 272", # SPRG0
78 "mfspr 4, 273", ] # SPRG1
79 initial_regs = [0] * 32
80 initial_sprs = {'SPRG0_priv': 0x12345678, 'SPRG1_priv': 0x5678,
81 }
82 self.add_case(Program(lst, bigendian),
83 initial_regs, initial_sprs)
84
85 def case_5_mtspr(self):
86 lst = ["mtspr 272, 1", # SPRG0
87 "mtspr 273, 2", # SPRG1
88 ]
89 initial_regs = [0] * 32
90 initial_regs[1] = 0x129518230011feed
91 initial_regs[2] = 0x123518230011fee0
92 initial_sprs = {'SPRG0_priv': 0x12345678, 'SPRG1_priv': 0x5678,
93 }
94 self.add_case(Program(lst, bigendian),
95 initial_regs, initial_sprs)
96
97 def case_6_set_tb(self):
98 lst = [ "mtspr 268, 2", # TB
99 "addi 1,0,0",
100 "addi 1,0,0",
101 "addi 1,0,0",
102 "addi 1,0,0",
103 "mfspr 1, 268", # TB
104 ]
105 initial_regs = [0] * 32
106 initial_regs[1] = 0x129518230011feed
107 initial_regs[2] = 0x123518230011fee0
108 initial_sprs = {'TB': 0x12345678,
109 }
110 self.add_case(Program(lst, bigendian),
111 initial_regs, initial_sprs)
112