3 This module implements the creation, inspection and comparison
4 of test states from different sources.
6 The basic premise is to create a test state using the TestState method.
7 The TestState method returns a test state object initialized with a
8 basic set of registers pulled from the 'to_test' object. The
9 state created can then be tested against other test states using the
12 The SimState class provides an example of needed registers and naming.
14 The TestState method relies on the 'state_factory' dictionary for lookup
15 of associated test class creation. The dictionary can be added to using
18 Also note when creating and accessing test state classes and object
19 methods, the use of yield from/yield is required.
25 from openpower
.decoder
.power_enums
import XER_bits
26 from openpower
.util
import log
31 yield from self
.get_intregs()
32 yield from self
.get_crregs()
33 yield from self
.get_xregs()
34 yield from self
.get_pc()
36 def compare(self
, s2
):
37 # Compare int registers
38 for i
, (self
.intregs
, s2
.intregs
) in enumerate(
39 zip(self
.intregs
, s2
.intregs
)):
40 log("asserting...reg", i
, self
.intregs
, s2
.intregs
)
41 log("code, frepr(code)", self
.code
, repr(self
.code
))
42 self
.dut
.assertEqual(self
.intregs
, s2
.intregs
,
43 "int reg %d (%s) not equal (%s) %s. got %x expected %x" %
44 (i
, self
.state_type
, s2
.state_type
, repr(self
.code
),
45 self
.intregs
, s2
.intregs
))
48 for i
, (self
.crregs
, s2
.crregs
) in enumerate(
49 zip(self
.crregs
, s2
.crregs
)):
50 log("asserting...cr", i
, self
.crregs
, s2
.crregs
)
51 self
.dut
.assertEqual(self
.crregs
, s2
.crregs
,
52 "cr reg %d (%s) not equal (%s) %s. got %x expected %x" %
53 (i
, self
.state_type
, s2
.state_type
, repr(self
.code
),
54 self
.crregs
, s2
.crregs
))
57 self
.dut
.assertEqual(self
.so
, s2
.so
, "so mismatch (%s != %s) %s" %
58 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
59 self
.dut
.assertEqual(self
.ov
, s2
.ov
, "ov mismatch (%s != %s) %s" %
60 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
61 self
.dut
.assertEqual(self
.ca
, s2
.ca
, "ca mismatch (%s != %s) %s" %
62 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
65 self
.dut
.assertEqual(self
.pc
, s2
.pc
, "pc mismatch (%s != %s) %s" %
66 (self
.state_type
, s2
.state_type
, repr(self
.code
)))
69 class SimState(State
):
70 def __init__(self
, sim
):
73 def get_intregs(self
):
78 simregval
= self
.sim
.gpr
[i
].asint()
79 self
.intregs
.append(simregval
)
80 log("class sim int regs", list(map(hex, self
.intregs
)))
87 cri
= self
.sim
.crl
[7 - i
].get_range().value
88 self
.crregs
.append(cri
)
89 log("class sim cr regs", list(map(hex, self
.crregs
)))
95 self
.so
= self
.sim
.spr
['XER'][XER_bits
['SO']].value
96 self
.ov
= self
.sim
.spr
['XER'][XER_bits
['OV']].value
97 self
.ov32
= self
.sim
.spr
['XER'][XER_bits
['OV32']].value
98 self
.ca
= self
.sim
.spr
['XER'][XER_bits
['CA']].value
99 self
.ca32
= self
.sim
.spr
['XER'][XER_bits
['CA32']].value
100 self
.ov
= self
.ov |
(self
.ov32
<< 1)
101 self
.ca
= self
.ca |
(self
.ca32
<< 1)
102 self
.xregs
.extend((self
.so
, self
.ov
, self
.ca
))
103 log("class sim xregs", list(map(hex, self
.xregs
)))
109 self
.pc
= self
.sim
.pc
.CIA
.value
110 self
.pcl
.append(self
.pc
)
111 log("class sim pc", hex(self
.pc
))
114 class ExpectedState(State
):
115 def __init__(self
, int_regs
= None, pc
= 0, crregs
= None,
116 so
= 0, ov
= 0, ca
=0):
119 if isinstance(int_regs
, int):
120 int_regs
= [0] * int_regs
121 self
.intregs
= int_regs
125 if isinstance(int_regs
, int):
126 crregs
= [0] * crregs
132 def get_intregs(self
): if False: yield
133 def get_crregs(self
): if False: yield
134 def get_xregs(self
): if False: yield
135 def get_pc(self
): if False: yield
139 state_factory
= {'sim': SimState
, 'expected': ExpectedState
}
142 def state_add(name
, kls
):
143 log("state_add", name
, kls
)
144 state_factory
[name
] = kls
147 def TestState(state_type
, to_test
, dut
, code
= 0):
148 state_class
= state_factory
[state_type
]
149 state
= state_class(to_test
)
150 state
.to_test
= to_test
152 state
.state_type
= state_type
154 yield from state
.get_state()
158 def teststate_check_regs(dut
, states
, test
, code
):
159 """teststate_check_regs: compares a set of Power ISA objects
160 to check if they have the same "state" (registers only, at the moment)
163 # create one TestState per "thing"
164 for stype
, totest
in states
.items():
165 state
= yield from TestState(stype
, totest
, dut
, code
)
167 # compare each "thing" against the next "thing" in the list.
168 # (no need to do an O(N^2) comparison here, they *all* have to be the same
169 for i
in range(len(slist
)-1):
170 state
, against
= slist
[i
], slist
[i
+1]
171 state
.compare(against
)