3 This module tests the functionality of the state class by manually
4 loading various registers and memory with values to be compared
5 between different states.
8 * https://bugs.libre-soc.org/show_bug.cgi?id=686
14 from openpower
.test
.state
import SimState
, state_factory
15 from soc
.simple
.test
.teststate
import HDLState
18 class TestStates(unittest
.TestCase
):
19 def test_basic_regs(self
):
20 initial_regs
= [0] * 32
22 initial_regs
[i
] = random
.randint(0, (1 << 64) - 1)
23 sim
= self
.empty_state('sim')
24 sim
.intregs
= initial_regs
25 hdl
= self
.empty_state('hdl')
26 hdl
.intregs
= initial_regs
28 sim
= self
.empty_state('sim')
29 sim
.intregs
= initial_regs
30 hdl
= self
.empty_state('hdl')
31 hdl
.intregs
= initial_regs
34 @unittest.expectedFailure
35 def test_basic_regs_fail(self
):
36 initial_regs
= [0] * 32
38 initial_regs
[i
] = random
.randint(0, (1 << 64) - 1)
39 fail_regs
[i
] = random
.randint(0, (1 << 64) - 1)
40 sim
= self
.empty_state('sim')
41 sim
.intregs
= initial_regs
42 hdl
= self
.empty_state('hdl')
43 hdl
.intregs
= fail_regs
45 sim
= self
.empty_state('sim')
46 sim
.intregs
= initial_regs
47 hdl
= self
.empty_state('hdl')
48 hdl
.intregs
= fail_regs
51 def test_basic_mem(self
):
54 initial_mem
[i
*8] = random
.randint(0, (1 << 64) - 1)
55 sim
= self
.empty_state('sim')
57 hdl
= self
.empty_state('hdl')
62 def test_basic_mem_size_0_diff(self
):
63 sim_mem
= {0: 8, 16: 24, 240: 32}
64 hdl_mem
= {0: 8, 16: 24, 224: 0, 232: 0, 240: 32}
65 sim
= self
.empty_state('sim')
67 hdl
= self
.empty_state('hdl')
72 @unittest.expectedFailure
73 def test_basic_mem_size_fail(self
):
76 initial_mem
[i
] = random
.randint(0, (1 << 64) - 1)
77 sim
= self
.empty_state('sim')
79 hdl
= self
.empty_state('hdl')
81 hdl
.mem
[i
] = initial_mem
[i
]
85 @unittest.expectedFailure
86 def test_basic_mem_off_by_one(self
):
87 sim_mem
= {0: 8, 16: 24, 24: 0}
88 hdl_mem
= {0: 8, 8: 24, 24: 0}
89 sim
= self
.empty_state('sim')
91 hdl
= self
.empty_state('hdl')
96 @unittest.expectedFailure
97 def test_basic_mem_one_word_fail(self
):
100 sim
= self
.empty_state('sim')
102 hdl
= self
.empty_state('hdl')
107 @unittest.expectedFailure
108 def test_basic_no_mem_fail(self
):
110 sim
= self
.empty_state('sim')
111 hdl
= self
.empty_state('hdl')
116 def empty_state(self
, state_type
):
117 state_class
= state_factory
[state_type
]
118 state
= state_class(None)
122 state
.so
, state
.sv
, state
.ov
, state
.ca
= 0, 0, 0, 0
126 state
.state_type
= state_type
130 if __name__
== '__main__':