3 This module tests the functionality of the state class by manually
4 loading various registers and memory with values to be compared
5 between different states.
8 * https://bugs.libre-soc.org/show_bug.cgi?id=686
14 from openpower
.test
.state
import SimState
, state_factory
17 class TestStates(unittest
.TestCase
):
18 @unittest.expectedFailure
# FIXME: KeyError: 'hdl'
19 def test_basic_regs(self
):
20 initial_regs
= [0] * 32
22 initial_regs
[i
] = random
.randint(0, (1 << 64) - 1)
23 sim
= self
.empty_state('sim')
24 sim
.intregs
= initial_regs
25 hdl
= self
.empty_state('hdl')
26 hdl
.intregs
= initial_regs
28 sim
= self
.empty_state('sim')
29 sim
.intregs
= initial_regs
30 hdl
= self
.empty_state('hdl')
31 hdl
.intregs
= initial_regs
34 @unittest.expectedFailure
35 def test_basic_regs_fail(self
):
36 initial_regs
= [0] * 32
38 initial_regs
[i
] = random
.randint(0, (1 << 64) - 1)
39 fail_regs
[i
] = random
.randint(0, (1 << 64) - 1)
40 sim
= self
.empty_state('sim')
41 sim
.intregs
= initial_regs
42 hdl
= self
.empty_state('hdl')
43 hdl
.intregs
= fail_regs
45 sim
= self
.empty_state('sim')
46 sim
.intregs
= initial_regs
47 hdl
= self
.empty_state('hdl')
48 hdl
.intregs
= fail_regs
51 @unittest.expectedFailure
# FIXME: KeyError: 'hdl'
52 def test_basic_mem(self
):
55 initial_mem
[i
*8] = random
.randint(0, (1 << 64) - 1)
56 sim
= self
.empty_state('sim')
58 hdl
= self
.empty_state('hdl')
63 @unittest.expectedFailure
# FIXME: KeyError: 'hdl'
64 def test_basic_mem_size_0_diff(self
):
65 sim_mem
= {0: 8, 16: 24, 240: 32}
66 hdl_mem
= {0: 8, 16: 24, 224: 0, 232: 0, 240: 32}
67 sim
= self
.empty_state('sim')
69 hdl
= self
.empty_state('hdl')
74 @unittest.expectedFailure
75 def test_basic_mem_size_fail(self
):
78 initial_mem
[i
] = random
.randint(0, (1 << 64) - 1)
79 sim
= self
.empty_state('sim')
81 hdl
= self
.empty_state('hdl')
83 hdl
.mem
[i
] = initial_mem
[i
]
87 @unittest.expectedFailure
88 def test_basic_mem_off_by_one(self
):
89 sim_mem
= {0: 8, 16: 24, 24: 0}
90 hdl_mem
= {0: 8, 8: 24, 24: 0}
91 sim
= self
.empty_state('sim')
93 hdl
= self
.empty_state('hdl')
98 @unittest.expectedFailure
99 def test_basic_mem_one_word_fail(self
):
102 sim
= self
.empty_state('sim')
104 hdl
= self
.empty_state('hdl')
109 @unittest.expectedFailure
110 def test_basic_no_mem_fail(self
):
112 sim
= self
.empty_state('sim')
113 hdl
= self
.empty_state('hdl')
118 def empty_state(self
, state_type
):
119 state_class
= state_factory
[state_type
]
120 state
= state_class(None)
124 state
.so
, state
.sv
, state
.ov
, state
.ca
= 0, 0, 0, 0
128 state
.state_type
= state_type
132 if __name__
== '__main__':