src/openpower/test/test_state_class.py

   1 """ Test States
   2
   3 This module tests the functionality of the state class by manually
   4 loading various registers and memory with values to be compared
   5 between different states.
   6
   7 related bugs:
   8     * https://bugs.libre-soc.org/show_bug.cgi?id=686
   9
  10 """
  11
  12 import unittest
  13 import random
  14 from openpower.test.state import SimState, state_factory
  15
  16
  17 class TestStates(unittest.TestCase):
  18     @unittest.expectedFailure  # FIXME: KeyError: 'hdl'
  19     def test_basic_regs(self):
  20         initial_regs = [0] * 32
  21         for i in range(32):
  22             initial_regs[i] = random.randint(0, (1 << 64) - 1)
  23         sim = self.empty_state('sim')
  24         sim.intregs = initial_regs
  25         hdl = self.empty_state('hdl')
  26         hdl.intregs = initial_regs
  27         sim.compare(hdl)
  28         sim = self.empty_state('sim')
  29         sim.intregs = initial_regs
  30         hdl = self.empty_state('hdl')
  31         hdl.intregs = initial_regs
  32         hdl.compare(sim)
  33
  34     @unittest.expectedFailure
  35     def test_basic_regs_fail(self):
  36         initial_regs = [0] * 32
  37         for i in range(32):
  38             initial_regs[i] = random.randint(0, (1 << 64) - 1)
  39             fail_regs[i] = random.randint(0, (1 << 64) - 1)
  40         sim = self.empty_state('sim')
  41         sim.intregs = initial_regs
  42         hdl = self.empty_state('hdl')
  43         hdl.intregs = fail_regs
  44         sim.compare(hdl)
  45         sim = self.empty_state('sim')
  46         sim.intregs = initial_regs
  47         hdl = self.empty_state('hdl')
  48         hdl.intregs = fail_regs
  49         hdl.compare(sim)
  50
  51     @unittest.expectedFailure  # FIXME: KeyError: 'hdl'
  52     def test_basic_mem(self):
  53         initial_mem = {}
  54         for i in range(32):
  55             initial_mem[i*8] = random.randint(0, (1 << 64) - 1)
  56         sim = self.empty_state('sim')
  57         sim.mem = initial_mem
  58         hdl = self.empty_state('hdl')
  59         hdl.mem = initial_mem
  60         sim.compare_mem(hdl)
  61         hdl.compare_mem(sim)
  62
  63     @unittest.expectedFailure  # FIXME: KeyError: 'hdl'
  64     def test_basic_mem_size_0_diff(self):
  65         sim_mem = {0: 8, 16: 24, 240: 32}
  66         hdl_mem = {0: 8, 16: 24, 224: 0, 232: 0, 240: 32}
  67         sim = self.empty_state('sim')
  68         sim.mem = sim_mem
  69         hdl = self.empty_state('hdl')
  70         hdl.mem = hdl_mem
  71         sim.compare_mem(hdl)
  72         hdl.compare_mem(sim)
  73
  74     @unittest.expectedFailure
  75     def test_basic_mem_size_fail(self):
  76         initial_mem = {}
  77         for i in range(32):
  78             initial_mem[i] = random.randint(0, (1 << 64) - 1)
  79         sim = self.empty_state('sim')
  80         sim.mem = initial_mem
  81         hdl = self.empty_state('hdl')
  82         for i in range(16):
  83             hdl.mem[i] = initial_mem[i]
  84         sim.compare_mem(hdl)
  85         hdl.compare_mem(sim)
  86
  87     @unittest.expectedFailure
  88     def test_basic_mem_off_by_one(self):
  89         sim_mem = {0: 8, 16: 24, 24: 0}
  90         hdl_mem = {0: 8, 8: 24, 24: 0}
  91         sim = self.empty_state('sim')
  92         sim.mem = sim_mem
  93         hdl = self.empty_state('hdl')
  94         hdl.mem = hdl_mem
  95         sim.compare_mem(hdl)
  96         hdl.compare_mem(sim)
  97
  98     @unittest.expectedFailure
  99     def test_basic_mem_one_word_fail(self):
 100         sim_mem = {0: 8}
 101         hdl_mem = {0: 16}
 102         sim = self.empty_state('sim')
 103         sim.mem = sim_mem
 104         hdl = self.empty_state('hdl')
 105         hdl.mem = hdl_mem
 106         sim.compare_mem(hdl)
 107         hdl.compare_mem(sim)
 108
 109     @unittest.expectedFailure
 110     def test_basic_no_mem_fail(self):
 111         hdl_mem = {16: 32}
 112         sim = self.empty_state('sim')
 113         hdl = self.empty_state('hdl')
 114         hdl.mem = hdl_mem
 115         sim.compare_mem(hdl)
 116         hdl.compare_mem(sim)
 117
 118     def empty_state(self, state_type):
 119         state_class = state_factory[state_type]
 120         state = state_class(None)
 121         state.intregs = []
 122         state.crregs = []
 123         state.pc = []
 124         state.so, state.sv, state.ov, state.ca = 0, 0, 0, 0
 125         state.mem = {}
 126         state.code = 0
 127         state.dut = self
 128         state.state_type = state_type
 129         return state
 130
 131
 132 if __name__ == '__main__':
 133     unittest.main()