add svp64 fptrans tests
[openpower-isa.git] / src / openpower / test / trap / trap_cases.py
1 from openpower.simulator.program import Program
2 from openpower.endian import bigendian
3 from openpower.consts import MSR
4 from openpower.test.state import ExpectedState
5
6 from openpower.test.common import TestAccumulatorBase
7 import random
8
9
10 class TrapTestCase(TestAccumulatorBase):
11
12 def case_1_kaivb(self):
13 # https://bugs.libre-soc.org/show_bug.cgi?id=859
14 lst = ["mtspr 850, 1", # KAIVB
15 "mfspr 2, 850",
16 ]
17 initial_regs = [0] * 32
18 initial_regs[1] = 0x129518230011feed
19 initial_sprs = {'KAIVB': 0x12345678,
20 }
21 msr = 0xa000000000000003
22 self.add_case(Program(lst, bigendian),
23 initial_regs, initial_sprs,
24 initial_msr=msr)
25
26 def case_2_kaivb_test(self):
27 # https://bugs.libre-soc.org/show_bug.cgi?id=859
28 # sets KAIVB to 1<<13 then deliberately causes exception.
29 # PC expected to jump to (1<<13)|0x700 *NOT* 0x700 as usual
30 lst = ["mtspr 850, 1", # KAIVB
31 "tbegin.", # deliberately use illegal instruction
32 ]
33 initial_regs = [0] * 32
34 initial_regs[1] = 1<<13
35 initial_sprs = {'KAIVB': 0x12345678,
36 }
37 msr = 0xa000000000000003
38 e = ExpectedState(pc=0x2700)
39 e.intregs[1] = 1<<13
40 e.msr = 0xa000000000000003 # TODO, not actually checked
41 self.add_case(Program(lst, bigendian),
42 initial_regs, initial_sprs,
43 initial_msr=msr,
44 expected=e)
45
46 def case_0_hrfid(self):
47 lst = ["hrfid"]
48 initial_regs = [0] * 32
49 initial_regs[1] = 1
50 initial_sprs = {'HSRR0': 0x12345678, 'HSRR1': 0x5678}
51 self.add_case(Program(lst, bigendian),
52 initial_regs, initial_sprs)
53
54 def case_1_rfid(self):
55 lst = ["rfid"]
56 initial_regs = [0] * 32
57 initial_regs[1] = 1
58 initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
59 self.add_case(Program(lst, bigendian),
60 initial_regs, initial_sprs)
61
62 def case_2_rfid(self):
63 lst = ["rfid"]
64 initial_regs = [0] * 32
65 initial_regs[1] = 1
66 initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0xb000000000001033}
67 e = ExpectedState(pc=0x700)
68 e.intregs[1] = 1
69 e.msr = 0xb000000000001033 # TODO, not actually checked
70 self.add_case(Program(lst, bigendian),
71 initial_regs, initial_sprs,
72 initial_msr=0xa000000000000003,
73 expected=e)
74
75 def case_0_trap_eq_imm(self):
76 insns = ["twi", "tdi"]
77 for i in range(2):
78 choice = random.choice(insns)
79 lst = [f"{choice} 4, 1, %d" % i] # TO=4: trap equal
80 initial_regs = [0] * 32
81 initial_regs[1] = 1
82 self.add_case(Program(lst, bigendian), initial_regs)
83
84 def case_0_trap_eq(self):
85 insns = ["tw", "td"]
86 for i in range(2):
87 choice = insns[i]
88 lst = [f"{choice} 4, 1, 2"] # TO=4: trap equal
89 initial_regs = [0] * 32
90 initial_regs[1] = 1
91 initial_regs[2] = 1
92 self.add_case(Program(lst, bigendian), initial_regs)
93
94 def case_3_mtmsr_0(self):
95 lst = ["mtmsr 1,0"]
96 initial_regs = [0] * 32
97 initial_regs[1] = 0xffffffffffffffff
98 self.add_case(Program(lst, bigendian), initial_regs)
99
100 def case_3_mtmsr_1(self):
101 lst = ["mtmsr 1,1"]
102 initial_regs = [0] * 32
103 initial_regs[1] = 0xffffffffffffffff
104 self.add_case(Program(lst, bigendian), initial_regs)
105
106 def case_4_mtmsrd_0_linux(self):
107 lst = ["mtmsrd 1,0"]
108 initial_regs = [0] * 32
109 initial_regs[1] = 0xb000000000001033
110 self.add_case(Program(lst, bigendian), initial_regs,
111 initial_msr=0xa000000000000003)
112
113 def case_4_mtmsrd_0(self):
114 lst = ["mtmsrd 1,0"]
115 initial_regs = [0] * 32
116 initial_regs[1] = 0xffffffffffffffff
117 self.add_case(Program(lst, bigendian), initial_regs)
118
119 def case_5_mtmsrd_1(self):
120 lst = ["mtmsrd 1,1"]
121 initial_regs = [0] * 32
122 initial_regs[1] = 0xffffffffffffffff
123 self.add_case(Program(lst, bigendian), initial_regs)
124
125 def case_6_mtmsr_priv_0(self):
126 lst = ["mtmsr 1,0"]
127 initial_regs = [0] * 32
128 initial_regs[1] = 0xffffffffffffffff
129 msr = 1 << MSR.PR # set in "problem state"
130 self.add_case(Program(lst, bigendian), initial_regs,
131 initial_msr=msr)
132
133 def case_7_rfid_priv_0(self):
134 lst = ["rfid"]
135 initial_regs = [0] * 32
136 initial_regs[1] = 1
137 initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
138 msr = 1 << MSR.PR # set in "problem state"
139 self.add_case(Program(lst, bigendian),
140 initial_regs, initial_sprs,
141 initial_msr=msr)
142
143 def case_8_mfmsr(self):
144 lst = ["mfmsr 1"]
145 initial_regs = [0] * 32
146 msr = (~(1 << MSR.PR)) & 0xffffffffffffffff
147 self.add_case(Program(lst, bigendian), initial_regs,
148 initial_msr=msr)
149
150 def case_9_mfmsr_priv(self):
151 lst = ["mfmsr 1"]
152 initial_regs = [0] * 32
153 msr = 1 << MSR.PR # set in "problem state"
154 self.add_case(Program(lst, bigendian), initial_regs,
155 initial_msr=msr)
156
157 def case_999_illegal(self):
158 # ok, um this is a bit of a cheat: use an instruction we know
159 # is not implemented by either ISACaller or the core
160 lst = ["tbegin.",
161 "mtmsr 1,1"] # should not get executed
162 initial_regs = [0] * 32
163 self.add_case(Program(lst, bigendian), initial_regs)
164