1 from openpower
.simulator
.program
import Program
2 from openpower
.endian
import bigendian
3 from openpower
.consts
import MSR
4 from openpower
.test
.state
import ExpectedState
6 from openpower
.test
.common
import TestAccumulatorBase
10 class TrapTestCase(TestAccumulatorBase
):
12 def case_1_kaivb(self
):
13 lst
= ["mtspr 850, 1", # KAIVB
16 initial_regs
= [0] * 32
17 initial_regs
[1] = 0x129518230011feed
18 initial_sprs
= {'KAIVB': 0x12345678,
20 msr
= 0xa000000000000003
21 self
.add_case(Program(lst
, bigendian
),
22 initial_regs
, initial_sprs
,
25 def case_0_hrfid(self
):
27 initial_regs
= [0] * 32
29 initial_sprs
= {'HSRR0': 0x12345678, 'HSRR1': 0x5678}
30 self
.add_case(Program(lst
, bigendian
),
31 initial_regs
, initial_sprs
)
33 def case_1_rfid(self
):
35 initial_regs
= [0] * 32
37 initial_sprs
= {'SRR0': 0x12345678, 'SRR1': 0x5678}
38 self
.add_case(Program(lst
, bigendian
),
39 initial_regs
, initial_sprs
)
41 def case_2_rfid(self
):
43 initial_regs
= [0] * 32
45 initial_sprs
= {'SRR0': 0x12345678, 'SRR1': 0xb000000000001033}
46 e
= ExpectedState(pc
=0x700)
48 e
.msr
= 0xb000000000001033 # TODO, not actually checked
49 self
.add_case(Program(lst
, bigendian
),
50 initial_regs
, initial_sprs
,
51 initial_msr
=0xa000000000000003,
54 def case_0_trap_eq_imm(self
):
55 insns
= ["twi", "tdi"]
57 choice
= random
.choice(insns
)
58 lst
= [f
"{choice} 4, 1, %d" % i
] # TO=4: trap equal
59 initial_regs
= [0] * 32
61 self
.add_case(Program(lst
, bigendian
), initial_regs
)
63 def case_0_trap_eq(self
):
67 lst
= [f
"{choice} 4, 1, 2"] # TO=4: trap equal
68 initial_regs
= [0] * 32
71 self
.add_case(Program(lst
, bigendian
), initial_regs
)
73 def case_3_mtmsr_0(self
):
75 initial_regs
= [0] * 32
76 initial_regs
[1] = 0xffffffffffffffff
77 self
.add_case(Program(lst
, bigendian
), initial_regs
)
79 def case_3_mtmsr_1(self
):
81 initial_regs
= [0] * 32
82 initial_regs
[1] = 0xffffffffffffffff
83 self
.add_case(Program(lst
, bigendian
), initial_regs
)
85 def case_4_mtmsrd_0_linux(self
):
87 initial_regs
= [0] * 32
88 initial_regs
[1] = 0xb000000000001033
89 self
.add_case(Program(lst
, bigendian
), initial_regs
,
90 initial_msr
=0xa000000000000003)
92 def case_4_mtmsrd_0(self
):
94 initial_regs
= [0] * 32
95 initial_regs
[1] = 0xffffffffffffffff
96 self
.add_case(Program(lst
, bigendian
), initial_regs
)
98 def case_5_mtmsrd_1(self
):
100 initial_regs
= [0] * 32
101 initial_regs
[1] = 0xffffffffffffffff
102 self
.add_case(Program(lst
, bigendian
), initial_regs
)
104 def case_6_mtmsr_priv_0(self
):
106 initial_regs
= [0] * 32
107 initial_regs
[1] = 0xffffffffffffffff
108 msr
= 1 << MSR
.PR
# set in "problem state"
109 self
.add_case(Program(lst
, bigendian
), initial_regs
,
112 def case_7_rfid_priv_0(self
):
114 initial_regs
= [0] * 32
116 initial_sprs
= {'SRR0': 0x12345678, 'SRR1': 0x5678}
117 msr
= 1 << MSR
.PR
# set in "problem state"
118 self
.add_case(Program(lst
, bigendian
),
119 initial_regs
, initial_sprs
,
122 def case_8_mfmsr(self
):
124 initial_regs
= [0] * 32
125 msr
= (~
(1 << MSR
.PR
)) & 0xffffffffffffffff
126 self
.add_case(Program(lst
, bigendian
), initial_regs
,
129 def case_9_mfmsr_priv(self
):
131 initial_regs
= [0] * 32
132 msr
= 1 << MSR
.PR
# set in "problem state"
133 self
.add_case(Program(lst
, bigendian
), initial_regs
,
136 def case_999_illegal(self
):
137 # ok, um this is a bit of a cheat: use an instruction we know
138 # is not implemented by either ISACaller or the core
140 "mtmsr 1,1"] # should not get executed
141 initial_regs
= [0] * 32
142 self
.add_case(Program(lst
, bigendian
), initial_regs
)