1 from openpower
.simulator
.program
import Program
2 from openpower
.endian
import bigendian
3 from openpower
.consts
import MSR
4 from openpower
.test
.state
import ExpectedState
6 from openpower
.test
.common
import TestAccumulatorBase
10 class TrapTestCase(TestAccumulatorBase
):
11 def case_1_kaivb(self
):
12 # https://bugs.libre-soc.org/show_bug.cgi?id=859
13 lst
= ["mtspr 850, 1", # KAIVB
16 initial_regs
= [0] * 32
17 initial_regs
[1] = 0x129518230011feed
18 initial_sprs
= {'KAIVB': 0x12345678,
20 msr
= 0xa000000000000003
21 self
.add_case(Program(lst
, bigendian
),
22 initial_regs
, initial_sprs
,
25 def case_2_kaivb_test(self
):
26 # https://bugs.libre-soc.org/show_bug.cgi?id=859
27 # sets KAIVB to 1<<13 then deliberately causes exception.
28 # PC expected to jump to (1<<13)|0x700 *NOT* 0x700 as usual
29 lst
= ["mtspr 850, 1", # KAIVB
30 "tbegin.", # deliberately use illegal instruction
32 initial_regs
= [0] * 32
33 initial_regs
[1] = 1 << 13
34 initial_sprs
= {'KAIVB': 0x12345678,
36 msr
= 0xa000000000000003
37 e
= ExpectedState(pc
=0x2700)
38 e
.intregs
[1] = 1 << 13
40 e
.sprs
['SRR1'] = 0xa000000000080003
41 e
.sprs
['KAIVB'] = 0x2000
42 e
.msr
= 0xa000000000000001
43 self
.add_case(Program(lst
, bigendian
),
44 initial_regs
, initial_sprs
,
48 def case_0_hrfid(self
):
50 initial_regs
= [0] * 32
52 initial_sprs
= {'HSRR0': 0x12345678, 'HSRR1': 0x5678}
53 self
.add_case(Program(lst
, bigendian
),
54 initial_regs
, initial_sprs
)
58 initial_regs
= [0] * 32
60 initial_sprs
= {'SRR0': 0x12345678, 'SRR1': 0x5678} # to overwrite
61 # expected results: PC should be at 0xc00 (sc address)
62 e
= ExpectedState(pc
=0xc00)
64 e
.sprs
['SRR0'] = 4 # PC to return to: CIA+4
65 e
.sprs
['SRR1'] = 0x9000000000022903 # MSR to restore after sc return
66 e
.msr
= 0x9000000000000001 # MSR changed to this by sc/trap
67 self
.add_case(Program(lst
, bigendian
),
68 initial_regs
, initial_sprs
,
71 def case_1_sc_rfid(self
):
72 # https://bugs.libre-soc.org/show_bug.cgi?id=982#c104
73 lst
= ["ba 3080" ] # branch to 0xc08
74 lst
+= ["addi 0,0,0"] * (0xbfc//4) # 0x004 to 0xbfc all NOP
75 lst
+= ["addi 3,0,3", # 0xc00 set r3=3 as return result from sc
77 "sc 0", # 0xc08 make syscall here
78 "addi 0,0,2", # 0xc0c checks that we returned here
80 initial_regs
= [0] * 32
82 initial_sprs
= {'SRR0': 0x12345678, 'SRR1': 0x5678} # to overwrite
83 # expected results: PC should be at 0xc00 (sc address)
84 e
= ExpectedState(pc
=0xc00)
85 e
.intregs
[3] = 3 # due to instruction at 0xc00
86 e
.intregs
[1] = 1 # should be unaltered
87 e
.intregs
[0] = 2 # due to instruction at 0xc0c
88 e
.sprs
['SRR0'] = 0xc0c # PC to return to: CIA+4 (0xc0c)
89 e
.sprs
['SRR1'] = 0xffff_ffff_ffff_ffff # MSR after rfid return
90 e
.msr
= 0xffffffffffffffff # MSR is restored (by rfid)
91 e
.pc
= 0xc10 # should stop after addi 0,0,2
92 self
.add_case(Program(lst
, bigendian
),
93 initial_regs
, initial_sprs
,
94 initial_msr
=0xffff_ffff_ffff_ffff,
97 def case_1_rfid(self
):
99 initial_regs
= [0] * 32
101 initial_sprs
= {'SRR0': 0x12345678, 'SRR1': 0x5678}
102 self
.add_case(Program(lst
, bigendian
),
103 initial_regs
, initial_sprs
)
105 def case_2_rfid(self
):
107 initial_regs
= [0] * 32
109 initial_sprs
= {'SRR0': 0x12345678, 'SRR1': 0xb000000000001033}
110 e
= ExpectedState(pc
=0x700)
112 e
.msr
= 0xb000000000001033 # TODO, not actually checked
113 self
.add_case(Program(lst
, bigendian
),
114 initial_regs
, initial_sprs
,
115 initial_msr
=0xa000000000000003,
118 def case_0_trap_eq_imm(self
):
119 insns
= ["twi", "tdi"]
121 choice
= random
.choice(insns
)
122 lst
= [f
"{choice} 4, 1, %d" % i
] # TO=4: trap equal
123 initial_regs
= [0] * 32
125 self
.add_case(Program(lst
, bigendian
), initial_regs
)
127 def case_0_trap_eq(self
):
131 lst
= [f
"{choice} 4, 1, 2"] # TO=4: trap equal
132 initial_regs
= [0] * 32
135 self
.add_case(Program(lst
, bigendian
), initial_regs
)
137 def case_3_mtmsr_0(self
):
139 initial_regs
= [0] * 32
140 initial_regs
[1] = 0xffffffffffffffff
141 self
.add_case(Program(lst
, bigendian
), initial_regs
)
143 def case_3_mtmsr_1(self
):
145 initial_regs
= [0] * 32
146 initial_regs
[1] = 0xffffffffffffffff
147 self
.add_case(Program(lst
, bigendian
), initial_regs
)
149 def case_4_mtmsrd_0_linux(self
):
151 initial_regs
= [0] * 32
152 initial_regs
[1] = 0xb000000000001033
153 self
.add_case(Program(lst
, bigendian
), initial_regs
,
154 initial_msr
=0xa000000000000003)
156 def case_4_mtmsrd_0(self
):
158 initial_regs
= [0] * 32
159 initial_regs
[1] = 0xffffffffffffffff
160 self
.add_case(Program(lst
, bigendian
), initial_regs
)
162 def case_5_mtmsrd_1(self
):
164 initial_regs
= [0] * 32
165 initial_regs
[1] = 0xffffffffffffffff
166 self
.add_case(Program(lst
, bigendian
), initial_regs
)
168 def case_6_mtmsr_priv_0(self
):
170 initial_regs
= [0] * 32
171 initial_regs
[1] = 0xffffffffffffffff
172 msr
= 1 << MSR
.PR
# set in "problem state"
173 self
.add_case(Program(lst
, bigendian
), initial_regs
,
176 def case_7_rfid_priv_0(self
):
178 initial_regs
= [0] * 32
180 initial_sprs
= {'SRR0': 0x12345678, 'SRR1': 0x5678}
181 msr
= 1 << MSR
.PR
# set in "problem state"
182 self
.add_case(Program(lst
, bigendian
),
183 initial_regs
, initial_sprs
,
186 def case_8_mfmsr(self
):
188 initial_regs
= [0] * 32
189 msr
= (~
(1 << MSR
.PR
)) & 0xffffffffffffffff
190 self
.add_case(Program(lst
, bigendian
), initial_regs
,
193 def case_9_mfmsr_priv(self
):
195 initial_regs
= [0] * 32
196 msr
= 1 << MSR
.PR
# set in "problem state"
197 self
.add_case(Program(lst
, bigendian
), initial_regs
,
200 def case_999_illegal(self
):
201 # ok, um this is a bit of a cheat: use an instruction we know
202 # is not implemented by either ISACaller or the core
204 "mtmsr 1,1"] # should not get executed
205 initial_regs
= [0] * 32
206 self
.add_case(Program(lst
, bigendian
), initial_regs
)