src/openpower/test/trap/trap_cases.py

   1 from openpower.simulator.program import Program
   2 from openpower.endian import bigendian
   3 from openpower.consts import MSR
   4 from openpower.test.state import ExpectedState
   5 from openpower.decoder.selectable_int import SelectableInt
   6 from openpower.test.common import TestAccumulatorBase
   7 import random
   8
   9
  10 class TrapTestCase(TestAccumulatorBase):
  11     def case_1_kaivb(self):
  12         # https://bugs.libre-soc.org/show_bug.cgi?id=859
  13         lst = ["mtspr 850, 1",  # KAIVB
  14                "mfspr 2, 850",
  15                ]
  16         initial_regs = [0] * 32
  17         initial_regs[1] = 0x129518230011feed
  18         initial_sprs = {'KAIVB': 0x12345678,
  19                         }
  20         msr = 0xa000000000000003
  21         self.add_case(Program(lst, bigendian),
  22                       initial_regs, initial_sprs,
  23                       initial_msr=msr)
  24
  25     def case_2_kaivb_test(self):
  26         # https://bugs.libre-soc.org/show_bug.cgi?id=859
  27         # sets KAIVB to 1<<13 then deliberately causes exception.
  28         # PC expected to jump to (1<<13)|0x700 *NOT* 0x700 as usual
  29         lst = ["mtspr 850, 1",  # KAIVB
  30                "tbegin.",       # deliberately use illegal instruction
  31                ]
  32         initial_regs = [0] * 32
  33         initial_regs[1] = 1 << 13
  34         initial_sprs = {'KAIVB': 0x12345678,
  35                         }
  36         msr = 0xa000000000000003
  37         e = ExpectedState(pc=0x2700)
  38         e.intregs[1] = 1 << 13
  39         e.sprs['SRR0'] = 0x4
  40         e.sprs['SRR1'] = 0xa000000000080003
  41         e.sprs['KAIVB'] = 0x2000
  42         e.msr = 0xa000000000000001
  43         self.add_case(Program(lst, bigendian),
  44                       initial_regs, initial_sprs,
  45                       initial_msr=msr,
  46                       expected=e)
  47
  48     def case_0_hrfid(self):
  49         lst = ["hrfid"]
  50         initial_regs = [0] * 32
  51         initial_regs[1] = 1
  52         initial_sprs = {'HSRR0': 0x12345678, 'HSRR1': 0x5678}
  53         self.add_case(Program(lst, bigendian),
  54                       initial_regs, initial_sprs)
  55
  56     def case_1_sc(self):
  57         lst = ["sc 0"]
  58         initial_regs = [0] * 32
  59         initial_regs[1] = 1
  60         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}  # to overwrite
  61         # expected results: PC should be at 0xc00 (sc address)
  62         e = ExpectedState(pc=0xc00)
  63         e.intregs[1] = 1
  64         e.sprs['SRR0'] = 4                  # PC to return to: CIA+4
  65         e.sprs['SRR1'] = 0x9000000000002903  # MSR to restore after sc return
  66         e.msr = 0x9000000000000001          # MSR changed to this by sc/trap
  67         self.add_case(Program(lst, bigendian),
  68                       initial_regs, initial_sprs,
  69                       expected=e)
  70
  71     def case_1_sc_rfid(self):
  72         # https://bugs.libre-soc.org/show_bug.cgi?id=982#c104
  73         lst = ["ba 3080" ]      # branch to 0xc08
  74         lst += ["addi 0,0,0"] * (0xbfc//4) # 0x004 to 0xbfc all NOP
  75         lst += ["addi 3,0,3",  # 0xc00 set r3=3 as return result from sc
  76                 "rfid",        # 0xc04
  77                 "sc 0",        # 0xc08 make syscall here
  78                 "addi 0,0,2",  # 0xc0c checks that we returned here
  79                 ]
  80         initial_regs = [0] * 32
  81         initial_regs[1] = 1
  82         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678} # to overwrite
  83         # expected results: PC should be at 0xc00 (sc address)
  84         e = ExpectedState(pc=0xc00)
  85         e.intregs[3] = 3 # due to instruction at 0xc00
  86         e.intregs[1] = 1 # should be unaltered
  87         e.intregs[0] = 2 # due to instruction at 0xc0c
  88         e.sprs['SRR0'] = 0xc0c              # PC to return to: CIA+4 (0xc0c)
  89         SRR1 = SelectableInt(-1, 64)
  90         SRR1[33:37] = 0 # sc clears bits 33:36
  91         SRR1[42:48] = 0 # sc clears bits 42:47
  92         e.sprs['SRR1'] = int(SRR1)         # MSR after rfid return
  93         e.msr = 0xffff_ffff_ffff_ffff      # MSR is restored (by rfid)
  94         e.pc = 0xc10                       # should stop after addi 0,0,2
  95         self.add_case(Program(lst, bigendian),
  96                       initial_regs, initial_sprs,
  97                       initial_msr=0xffff_ffff_ffff_ffff,
  98                       expected=e)
  99
 100     def case_1_rfid(self):
 101         lst = ["rfid"]
 102         initial_regs = [0] * 32
 103         initial_regs[1] = 1
 104         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
 105         self.add_case(Program(lst, bigendian),
 106                       initial_regs, initial_sprs)
 107
 108     def case_2_rfid(self):
 109         lst = ["rfid"]
 110         initial_regs = [0] * 32
 111         initial_regs[1] = 1
 112         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0xb000000000001033}
 113         e = ExpectedState(pc=0x700)
 114         e.intregs[1] = 1
 115         e.msr = 0xb000000000001033  # TODO, not actually checked
 116         self.add_case(Program(lst, bigendian),
 117                       initial_regs, initial_sprs,
 118                       initial_msr=0xa000000000000003,
 119                       expected=e)
 120
 121     def case_0_trap_eq_imm(self):
 122         insns = ["twi", "tdi"]
 123         for i in range(2):
 124             choice = random.choice(insns)
 125             lst = [f"{choice} 4, 1, %d" % i]  # TO=4: trap equal
 126             initial_regs = [0] * 32
 127             initial_regs[1] = 1
 128             self.add_case(Program(lst, bigendian), initial_regs)
 129
 130     def case_0_trap_eq(self):
 131         insns = ["tw", "td"]
 132         for i in range(2):
 133             choice = insns[i]
 134             lst = [f"{choice} 4, 1, 2"]  # TO=4: trap equal
 135             initial_regs = [0] * 32
 136             initial_regs[1] = 1
 137             initial_regs[2] = 1
 138             self.add_case(Program(lst, bigendian), initial_regs)
 139
 140     def case_3_mtmsr_0(self):
 141         lst = ["mtmsr 1,0"]
 142         initial_regs = [0] * 32
 143         initial_regs[1] = 0xffffffffffffffff
 144         self.add_case(Program(lst, bigendian), initial_regs)
 145
 146     def case_3_mtmsr_1(self):
 147         lst = ["mtmsr 1,1"]
 148         initial_regs = [0] * 32
 149         initial_regs[1] = 0xffffffffffffffff
 150         self.add_case(Program(lst, bigendian), initial_regs)
 151
 152     def case_4_mtmsrd_0_linux(self):
 153         lst = ["mtmsrd 1,0"]
 154         initial_regs = [0] * 32
 155         initial_regs[1] = 0xb000000000001033
 156         self.add_case(Program(lst, bigendian), initial_regs,
 157                       initial_msr=0xa000000000000003)
 158
 159     def case_4_mtmsrd_0(self):
 160         lst = ["mtmsrd 1,0"]
 161         initial_regs = [0] * 32
 162         initial_regs[1] = 0xffffffffffffffff
 163         self.add_case(Program(lst, bigendian), initial_regs)
 164
 165     def case_5_mtmsrd_1(self):
 166         lst = ["mtmsrd 1,1"]
 167         initial_regs = [0] * 32
 168         initial_regs[1] = 0xffffffffffffffff
 169         self.add_case(Program(lst, bigendian), initial_regs)
 170
 171     def case_6_mtmsr_priv_0(self):
 172         lst = ["mtmsr 1,0"]
 173         initial_regs = [0] * 32
 174         initial_regs[1] = 0xffffffffffffffff
 175         msr = 1 << MSR.PR  # set in "problem state"
 176         self.add_case(Program(lst, bigendian), initial_regs,
 177                       initial_msr=msr)
 178
 179     def case_7_rfid_priv_0(self):
 180         lst = ["rfid"]
 181         initial_regs = [0] * 32
 182         initial_regs[1] = 1
 183         initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
 184         msr = 1 << MSR.PR  # set in "problem state"
 185         self.add_case(Program(lst, bigendian),
 186                       initial_regs, initial_sprs,
 187                       initial_msr=msr)
 188
 189     def case_8_mfmsr(self):
 190         lst = ["mfmsr 1"]
 191         initial_regs = [0] * 32
 192         msr = (~(1 << MSR.PR)) & 0xffffffffffffffff
 193         self.add_case(Program(lst, bigendian), initial_regs,
 194                       initial_msr=msr)
 195
 196     def case_9_mfmsr_priv(self):
 197         lst = ["mfmsr 1"]
 198         initial_regs = [0] * 32
 199         msr = 1 << MSR.PR  # set in "problem state"
 200         self.add_case(Program(lst, bigendian), initial_regs,
 201                       initial_msr=msr)
 202
 203     def case_999_illegal(self):
 204         # ok, um this is a bit of a cheat: use an instruction we know
 205         # is not implemented by either ISACaller or the core
 206         lst = ["tbegin.",
 207                "mtmsr 1,1"]  # should not get executed
 208         initial_regs = [0] * 32
 209         self.add_case(Program(lst, bigendian), initial_regs)