1 """useful function for emulating a wishbone interface
3 from nmigen
.sim
import Settle
7 def wb_get_classic(wb
, mem
, name
=None):
8 """simulator process for emulating wishbone (classic) out of a dictionary
14 assert (stop
== False)
17 while True: # wait for dc_valid
25 addr
= (yield wb
.adr
) << 3
27 print (" %s WB NO entry @ %x, returning zero" % \
34 store
= (yield wb
.dat_w
)
36 data
= mem
.get(addr
, 0)
37 # note we assume 8-bit sel, here
46 print (" %s WB set %x mask %x data %x" % (name
, addr
, sel
, res
))
49 data
= mem
.get(addr
, 0)
50 yield wb
.dat_r
.eq(data
)
51 print (" %s WB get %x data %x" % (name
, addr
, data
))
53 # a dumb "single-ack", this is non-pipeline
60 def wb_get(wb
, mem
, name
=None):
61 """simulator process for emulating wishbone (pipelined) out of a dictionary
62 deliberately do not send back a stall (ever)
68 assert (stop
== False)
71 while True: # wait for dc_valid
84 addr
= (yield wb
.adr
) << 3
86 print (" %s WB NO entry @ %x, returning zero" % \
89 print (" %s WB req @ %x" % (name
, addr
))
95 store
= (yield wb
.dat_w
)
97 data
= mem
.get(addr
, 0)
98 # note we assume 8-bit sel, here
107 print (" %s WB set %x mask %x data %x" % \
108 (name
, addr
, sel
, res
))
112 data
= mem
.get(prev_addr
, 0)
113 yield wb
.dat_r
.eq(data
)
114 print (" %s WB get %x data %x" % \
115 (name
, prev_addr
, data
))
117 # acknowledge previous strobe 1 clock late
118 yield wb
.ack
.eq(next_ack
)
124 # clear ack for next cyc