src/openpower/test/wb_get.py

   1 """useful function for emulating a wishbone interface
   2 """
   3 from nmigen.sim import Settle
   4
   5 stop = False
   6
   7 def wb_get_classic(wb, mem, name=None):
   8     """simulator process for emulating wishbone (classic) out of a dictionary
   9     """
  10     if name is None:
  11         name = ""
  12
  13     global stop
  14     assert (stop == False)
  15
  16     while not stop:
  17         while True: # wait for dc_valid
  18             if stop:
  19                 return
  20             cyc = yield (wb.cyc)
  21             stb = yield (wb.stb)
  22             if cyc and stb:
  23                 break
  24             yield
  25         addr = (yield wb.adr) << 3
  26         if addr not in mem:
  27             print ("    %s WB NO entry @ %x, returning zero" % \
  28                         (name, addr))
  29
  30         # read or write?
  31         we = (yield wb.we)
  32         if we:
  33             # WRITE
  34             store = (yield wb.dat_w)
  35             sel = (yield wb.sel)
  36             data = mem.get(addr, 0)
  37             # note we assume 8-bit sel, here
  38             res = 0
  39             for i in range(8):
  40                 mask = 0xff << (i*8)
  41                 if sel & (1<<i):
  42                     res |= store & mask
  43                 else:
  44                     res |= data & mask
  45             mem[addr] = res
  46             print ("    %s WB set %x mask %x data %x" % (name, addr, sel, res))
  47         else:
  48             # READ
  49             data = mem.get(addr, 0)
  50             yield wb.dat_r.eq(data)
  51             print ("    %s WB get %x data %x" % (name, addr, data))
  52
  53         # a dumb "single-ack", this is non-pipeline
  54         yield wb.ack.eq(1)
  55         yield
  56         yield wb.ack.eq(0)
  57         yield
  58
  59
  60 def wb_get(wb, mem, name=None):
  61     """simulator process for emulating wishbone (pipelined) out of a dictionary
  62     deliberately do not send back a stall (ever)
  63     """
  64     if name is None:
  65         name = ""
  66
  67     global stop
  68     assert (stop == False)
  69
  70     while not stop:
  71         while True: # wait for dc_valid
  72             if stop:
  73                 return
  74             cyc = yield (wb.cyc)
  75             stb = yield (wb.stb)
  76             if cyc and stb:
  77                 break
  78             yield
  79
  80         next_ack = 0
  81         addr = 0
  82         while cyc:
  83             prev_addr = addr
  84             addr = (yield wb.adr) << 3
  85             if addr not in mem:
  86                 print ("    %s WB NO entry @ %x, returning zero" % \
  87                             (name, addr))
  88
  89             print ("    %s WB req @ %x" % (name, addr))
  90
  91             # read or write?
  92             we = (yield wb.we)
  93             if we:
  94                 # WRITE
  95                 store = (yield wb.dat_w)
  96                 sel = (yield wb.sel)
  97                 data = mem.get(addr, 0)
  98                 # note we assume 8-bit sel, here
  99                 res = 0
 100                 for i in range(8):
 101                     mask = 0xff << (i*8)
 102                     if sel & (1<<i):
 103                         res |= store & mask
 104                     else:
 105                         res |= data & mask
 106                 mem[addr] = res
 107                 print ("    %s WB set %x mask %x data %x" % \
 108                             (name, addr, sel, res))
 109             else:
 110                 # READ
 111                 if next_ack:
 112                     data = mem.get(prev_addr, 0)
 113                     yield wb.dat_r.eq(data)
 114                     print ("    %s WB get %x data %x" % \
 115                                     (name, prev_addr, data))
 116
 117             # acknowledge previous strobe 1 clock late
 118             yield wb.ack.eq(next_ack)
 119             yield
 120             next_ack = stb
 121             stb = yield (wb.stb)
 122             cyc = yield (wb.cyc)
 123
 124         # clear ack for next cyc
 125         yield wb.ack.eq(0)
 126
 127