1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
18 # default module imports
24 # project module imports
25 from interface_decl
import *
26 from interface_def
import *
28 from wire_def
import *
29 from actual_pinmux
import *
30 from bus_transactors
import *
32 if not os
.path
.exists("bsv_src"):
33 os
.makedirs("bsv_src")
37 This BSV file has been generated by the PinMux tool available at:
38 https://bitbucket.org/casl/pinmux.
40 Authors: Neel Gala, Luke
41 Date of generation: ''' + time
.strftime("%c") + '''
44 header
= copyright
+'''
48 Bit#(1) outputval; // output from core to pad bit7
49 Bit#(1) output_en; // output enable from core to pad bit6
50 Bit#(1) input_en; // input enable from core to io_cell bit5
51 Bit#(1) pullup_en; // pullup enable from core to io_cell bit4
52 Bit#(1) pulldown_en; // pulldown enable from core to io_cell bit3
53 Bit#(1) drivestrength; // drivestrength from core to io_cell bit2
54 Bit#(1) pushpull_en; // pushpull enable from core to io_cell bit1
55 Bit#(1) opendrain_en; // opendrain enable form core to io_cell bit0
56 } GenericIOType deriving(Eq,Bits,FShow);
58 interface MuxSelectionLines;
65 # ============================================#
66 # ==== populating the file with the code =====#
67 # ============================================#
69 # package and interface declaration followed by the generic io_cell definition
70 with
open("./bsv_src/pinmux.bsv", "w") as bsv_file
:
71 bsv_file
.write(header
)
75 // declare the method which will capture the user pin-mux
76 // selection values.The width of the input is dependent on the number
77 // of muxes happening per IO. For now we have a generalized width
78 // where each IO will have the same number of muxes.''')
80 for cell
in muxed_cells
:
81 bsv_file
.write(mux_interface
.ifacefmt(cell
[0],
82 int(math
.log(len(cell
) - 1, 2))))
87 interface PeripheralSide;
88 // declare the interface to the IO cells.
89 // Each IO cell will have 8 input field (output from pin mux
90 // and on output field (input to pinmux)''')
91 for i
in range(0, N_IO
):
92 bsv_file
.write('''\n // interface for IO CEll-{0}''')
93 bsv_file
.write(io_interface
.ifacefmt(i
))
94 # ==============================================================
96 # == create method definitions for all peripheral interfaces ==#
97 ifaces
.ifacefmt(bsv_file
)
99 # ==============================================================
101 # ===== finish interface definition and start module definition=======
105 interface Ifc_pinmux;
106 interface MuxSelectionLines mux_lines;
107 interface PeripheralSide peripheral_side;
110 module mkpinmux(Ifc_pinmux);
112 # ====================================================================
114 # ======================= create wire and registers =================#
116 // the followins wires capture the pin-mux selection
117 // values for each mux assigned to a CELL
119 for cell
in muxed_cells
:
120 bsv_file
.write(muxwire
.format(cell
[0], int(math
.log(len(cell
) - 1, 2))))
124 '''\n // following wires capture the values sent to the IO Cell''')
125 for i
in range(0, N_IO
):
126 bsv_file
.write(generic_io
.format(i
))
128 ifaces
.wirefmt(bsv_file
)
131 # ====================================================================
132 # ========================= Actual pinmuxing ========================#
134 /*====== This where the muxing starts for each io-cell======*/
136 bsv_file
.write(pinmux
)
138 /*============================================================*/
140 # ====================================================================
141 # ================= interface definitions for each method =============#
143 interface mux_lines = interface MuxSelectionLines
145 for cell
in muxed_cells
:
146 bsv_file
.write(mux_interface
.ifacedef(cell
[0],
147 int(math
.log(len(cell
) - 1, 2))))
150 interface peripheral_side = interface PeripheralSide
152 for i
in range(0, N_IO
):
153 bsv_file
.write(io_interface
.ifacedef(i
))
154 ifaces
.ifacedef(bsv_file
)
155 bsv_file
.write(footer
)
156 print("BSV file successfully generated: bsv_src/pinmux.bsv")
157 # ======================================================================
159 with
open('bsv_src/PinTop.bsv', 'w') as bsv_file
:
160 bsv_file
.write(copyright
+'''
163 interface Ifc_PintTop;
164 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
165 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
166 interface PeripheralSide peripheral_side;
169 module mkPinTop(Ifc_PintTop);
170 // instantiate the pin-mux module here
171 Ifc_pinmux pinmux <-mkpinmux;
173 // declare the registers which will be used to mux the IOs
174 '''.format(ADDR_WIDTH
, DATA_WIDTH
))
176 for cell
in muxed_cells
:
178 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
179 int(math
.log(len(cell
) - 1, 2)), cell
[0]))
182 // rule to connect the registers to the selection lines of the
184 rule connect_selection_registers;''')
186 for cell
in muxed_cells
:
188 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell
[0]))
192 // method definitions for the write user interface
193 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
195 case (addr[{0}:{1}])'''.format(upper_offset
, lower_offset
,
196 ADDR_WIDTH
, DATA_WIDTH
))
198 for cell
in muxed_cells
:
200 {0}: rg_muxio_{1}<=truncate(data);'''.format(index
, cell
[0]))
210 // method definitions for the read user interface
211 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
214 case (addr[{0}:{1}])'''.format(upper_offset
, lower_offset
,
215 ADDR_WIDTH
, DATA_WIDTH
))
217 for cell
in muxed_cells
:
219 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index
, cell
[0]))
225 return tuple2(err,data);
227 interface peripheral_side=pinmux.peripheral_side;
232 # ######## Generate bus transactors ################
233 with
open('bsv_src/bus.bsv', 'w') as bsv_file
:
234 bsv_file
.write(axi4_lite
.format(ADDR_WIDTH
, DATA_WIDTH
))
235 # ##################################################