1 // Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
2 // Copyright (c) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 module simsoc_hyperram_tb;
7 // GSR & PUR init requires for Lattice models
21 // Generate 100 Mhz clock
46 .TimingModel("S27KL0641DABHI000"))
62 // uart, LEDs, switches
84 .hyperram_0__cs_n__io(o_csn0),
85 .hyperram_0__rst_n__io(o_resetn),
86 .hyperram_0__rwds__io(io_rwds),
87 .hyperram_0__ck__io(o_clk),
88 .hyperram_0__dq__io(io_dq),
90 //.spi_flash_4x_0__dq__io(io_spi_dq),
91 //.spi_flash_4x_0__cs__io(spi_cs_n),
92 .spi_0_0__dq__io(io_spi_dq),
93 .spi_0_0__cs_n__io(spi_cs_n),
96 .uart_0__rx__io(uart_rx),
97 .uart_0__tx__io(uart_tx),
108 //.switch_0__io(switch_0),
109 //.switch_1__io(switch_1),
110 //.switch_2__io(switch_2),
111 //.switch_3__io(switch_3),
112 //.switch_4__io(switch_4),
113 //.switch_5__io(switch_5),
114 //.switch_6__io(switch_6),
115 //.switch_7__io(switch_7),
121 cy15b104qs cy15b104qs
124 .SCK(simsoctop.spi0.spi_clk),
125 .RESETNeg(io_spi_dq[3]),
133 $dumpfile("simsoc_hyperram.fst");
135 $dumpvars(0, o_resetn);
136 $dumpvars(0, o_csn0);
138 $dumpvars(0, io_rwds);
140 $dumpvars(0, uart_tx);
141 $dumpvars(0, uart_rx);
142 $dumpvars(0, simsoctop);
148 // run for a set time period then exit