src/simsoc_hyperram_tb.v

   1 // Copyright (c) 2020 LambdaConcept <contact@lambdaconcept.com>
   2 // Copyright (c) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3
   4 `timescale 1 ns / 1 ns
   5
   6 module simsoc_hyperram_tb;
   7   // GSR & PUR init requires for Lattice models
   8   GSR GSR_INST (
   9     .GSR(1'b1)
  10   );
  11   PUR PUR_INST (
  12     .PUR (1'b1)
  13   );
  14
  15   reg clkin;
  16   wire sync;
  17   wire sync2x;
  18   wire dramsync;
  19   wire init;
  20
  21   // Generate 100 Mhz clock
  22   always
  23     begin
  24       clkin = 1;
  25       #5;
  26       clkin = 0;
  27       #5;
  28     end
  29
  30     // Outputs
  31     wire o_csn0;
  32     wire o_clk;
  33     wire o_resetn;
  34
  35     // Bidirs
  36     wire [7:0] io_dq;
  37     wire io_rwds;
  38
  39     // SPI
  40     wire spi_cs_n;
  41     wire spi_rst_n;
  42     wire [3:0] io_spi_dq;
  43
  44 s27kl0641
  45     #(
  46     .TimingModel("S27KL0641DABHI000"))
  47     hyperram (
  48     .DQ7(io_dq[7]),
  49     .DQ6(io_dq[6]),
  50     .DQ5(io_dq[5]),
  51     .DQ4(io_dq[4]),
  52     .DQ3(io_dq[3]),
  53     .DQ2(io_dq[2]),
  54     .DQ1(io_dq[1]),
  55     .DQ0(io_dq[0]),
  56     .RWDS(io_rwds),
  57     .CSNeg(o_csn0),
  58     .CK(o_clk),
  59     .RESETNeg(o_resetn)
  60     );
  61
  62   // uart, LEDs, switches
  63   wire uart_tx ;
  64   reg uart_rx = 0;
  65   wire led_0;
  66   wire led_1;
  67   wire led_2;
  68   wire led_3;
  69   wire led_4;
  70   wire led_5;
  71   wire led_6;
  72   wire led_7;
  73   //reg switch_0 = 0;
  74   //reg switch_1 = 0;
  75   //reg switch_2 = 0;
  76   //reg switch_3 = 0;
  77   //reg switch_4 = 0;
  78   //reg switch_5 = 0;
  79   //reg switch_6 = 0;
  80   //reg switch_7 = 0;
  81
  82   top simsoctop (
  83     // hyperram
  84     .hyperram_0__cs_n__io(o_csn0),
  85     .hyperram_0__rst_n__io(o_resetn),
  86     .hyperram_0__rwds__io(io_rwds),
  87     .hyperram_0__ck__io(o_clk),
  88     .hyperram_0__dq__io(io_dq),
  89     // Quad SPI
  90     //.spi_flash_4x_0__dq__io(io_spi_dq),
  91     //.spi_flash_4x_0__cs__io(spi_cs_n),
  92     .spi_0_0__dq0__io(io_spi_dq[0]),
  93     .spi_0_0__dq1__io(io_spi_dq[1]),
  94     .spi_0_0__dq2__io(io_spi_dq[2]),
  95     .spi_0_0__dq3__io(io_spi_dq[3]),
  96     .spi_0_0__cs_n__io(spi_cs_n),
  97
  98     // uart
  99     .uart_0__rx__io(uart_rx),
 100     .uart_0__tx__io(uart_tx),
 101     // led
 102     .led_0__io(led_0),
 103     .led_1__io(led_1),
 104     .led_2__io(led_2),
 105     .led_3__io(led_3),
 106     .led_4__io(led_4),
 107     .led_5__io(led_5),
 108     .led_6__io(led_6),
 109     .led_7__io(led_7),
 110     // switches
 111     //.switch_0__io(switch_0),
 112     //.switch_1__io(switch_1),
 113     //.switch_2__io(switch_2),
 114     //.switch_3__io(switch_3),
 115     //.switch_4__io(switch_4),
 116     //.switch_5__io(switch_5),
 117     //.switch_6__io(switch_6),
 118     //.switch_7__io(switch_7),
 119     // clock/reset
 120     .clk100_0__p(clkin),
 121     .rst_0__io(1'b0)
 122   );
 123
 124     cy15b104qs
 125     #(
 126     .mem_file_name("firmware.hex"))
 127      cy15b104qs
 128      (
 129       .CSNeg(spi_cs_n),
 130       .SCK(simsoctop.spi0.spi_clk),
 131       .RESETNeg(io_spi_dq[3]),
 132       .SI(io_spi_dq[0]),
 133       .SO(io_spi_dq[1]),
 134       .WPNeg(io_spi_dq[2])
 135       );
 136
 137   initial
 138     begin
 139       $dumpfile("simsoc_hyperram.fst");
 140       $dumpvars(0, clkin);
 141       $dumpvars(0, o_resetn);
 142       $dumpvars(0, o_csn0);
 143       $dumpvars(0, o_clk);
 144       $dumpvars(0, io_rwds);
 145       $dumpvars(0, io_dq);
 146       $dumpvars(0, uart_tx);
 147       $dumpvars(0, uart_rx);
 148       $dumpvars(0, simsoctop);
 149       $dumpvars(0, cy15b104qs);
 150     end
 151
 152   initial
 153     begin
 154
 155       // run for a set time period then exit
 156       #120000000;
 157
 158       $finish;
 159     end
 160
 161 endmodule