57e7825254b611650705487d7592f8428156f0f8
1 from functools
import wraps
2 from soc
.decoder
.orderedset
import OrderedSet
3 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
5 from soc
.decoder
.power_enums
import spr_dict
, XER_bits
6 from soc
.decoder
.helpers
import exts
7 from collections
import namedtuple
10 instruction_info
= namedtuple('instruction_info',
11 'func read_regs uninit_regs write_regs ' + \
12 'special_regs op_fields form asmregs')
22 def create_args(reglist
, extra
=None):
34 def __init__(self
, bytes_per_word
=8):
36 self
.bytes_per_word
= bytes_per_word
37 self
.word_log2
= math
.ceil(math
.log2(bytes_per_word
))
39 def _get_shifter_mask(self
, width
, remainder
):
40 shifter
= ((self
.bytes_per_word
- width
) - remainder
) * \
42 mask
= (1 << (width
* 8)) - 1
45 # TODO: Implement ld/st of lesser width
46 def ld(self
, address
, width
=8):
47 remainder
= address
& (self
.bytes_per_word
- 1)
48 address
= address
>> self
.word_log2
49 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
50 if address
in self
.mem
:
51 val
= self
.mem
[address
]
55 if width
!= self
.bytes_per_word
:
56 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
57 val
= val
& (mask
<< shifter
)
59 print("Read {:x} from addr {:x}".format(val
, address
))
62 def st(self
, address
, value
, width
=8):
63 remainder
= address
& (self
.bytes_per_word
- 1)
64 address
= address
>> self
.word_log2
65 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
66 print("Writing {:x} to addr {:x}".format(value
, address
))
67 if width
!= self
.bytes_per_word
:
68 if address
in self
.mem
:
69 val
= self
.mem
[address
]
72 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
73 val
&= ~
(mask
<< shifter
)
74 val |
= value
<< shifter
75 self
.mem
[address
] = val
77 self
.mem
[address
] = value
79 def __call__(self
, addr
, sz
):
80 val
= self
.ld(addr
.value
, sz
)
81 print ("memread", addr
, sz
, val
)
82 return SelectableInt(val
, sz
*8)
84 def memassign(self
, addr
, sz
, val
):
85 print ("memassign", addr
, sz
, val
)
86 self
.st(addr
.value
, val
.value
, sz
)
90 def __init__(self
, decoder
, regfile
):
94 self
[i
] = SelectableInt(regfile
[i
], 64)
96 def __call__(self
, ridx
):
99 def set_form(self
, form
):
102 def getz(self
, rnum
):
103 #rnum = rnum.value # only SelectableInt allowed
104 print("GPR getzero", rnum
)
106 return SelectableInt(0, 64)
109 def _get_regnum(self
, attr
):
110 getform
= self
.sd
.sigforms
[self
.form
]
111 rnum
= getattr(getform
, attr
)
114 def ___getitem__(self
, attr
):
115 print("GPR getitem", attr
)
116 rnum
= self
._get
_regnum
(attr
)
117 return self
.regfile
[rnum
]
120 for i
in range(0, len(self
), 8):
123 s
.append("%08x" % self
[i
+j
].value
)
125 print("reg", "%2d" % i
, s
)
128 def __init__(self
, pc_init
=0):
129 self
.CIA
= SelectableInt(pc_init
, 64)
130 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
132 def update(self
, namespace
):
133 self
.CIA
= namespace
['NIA'].narrow(64)
134 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
135 namespace
['CIA'] = self
.CIA
136 namespace
['NIA'] = self
.NIA
140 def __init__(self
, dec2
, initial_sprs
={}):
143 self
.update(initial_sprs
)
145 def __getitem__(self
, key
):
146 # if key in special_sprs get the special spr, otherwise return key
147 if isinstance(key
, SelectableInt
):
149 key
= special_sprs
.get(key
, key
)
151 return dict.__getitem
__(self
, key
)
154 return SelectableInt(0, info
.length
)
156 def __setitem__(self
, key
, value
):
157 if isinstance(key
, SelectableInt
):
159 key
= special_sprs
.get(key
, key
)
160 dict.__setitem
__(self
, key
, value
)
162 def __call__(self
, ridx
):
168 # decoder2 - an instance of power_decoder2
169 # regfile - a list of initial values for the registers
170 def __init__(self
, decoder2
, regfile
, initial_sprs
={}, initial_cr
=0):
171 self
.gpr
= GPR(decoder2
, regfile
)
174 self
.spr
= SPR(decoder2
, initial_sprs
)
176 # FPR (same as GPR except for FP nums)
177 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
178 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
179 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
180 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
182 # 2.3.2 LR (actually SPR #8) -- Done
183 # 2.3.3 CTR (actually SPR #9) -- Done
184 # 2.3.4 TAR (actually SPR #815)
185 # 3.2.2 p45 XER (actually SPR #1) -- Done
186 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
188 # create CR then allow portions of it to be "selectable" (below)
189 self
._cr
= SelectableInt(initial_cr
, 64) # underlying reg
190 self
.cr
= FieldSelectableInt(self
._cr
, list(range(32,64)))
192 # "undefined", just set to variable-bit-width int (use exts "max")
193 self
.undefined
= SelectableInt(0, 256) # TODO, not hard-code 256!
195 self
.namespace
= {'GPR': self
.gpr
,
198 'memassign': self
.memassign
,
202 'undefined': self
.undefined
,
203 'mode_is_64bit': True,
207 # field-selectable versions of Condition Register TODO check bitranges?
210 bits
= tuple(range(i
*4, (i
+1)*4))# errr... maybe?
211 _cr
= FieldSelectableInt(self
.cr
, bits
)
213 self
.namespace
["CR%d" % i
] = _cr
215 self
.decoder
= decoder2
.dec
218 def memassign(self
, ea
, sz
, val
):
219 self
.mem
.memassign(ea
, sz
, val
)
221 def prep_namespace(self
, formname
, op_fields
):
222 # TODO: get field names from form in decoder*1* (not decoder2)
223 # decoder2 is hand-created, and decoder1.sigform is auto-generated
225 # then "yield" fields only from op_fields rather than hard-coded
227 fields
= self
.decoder
.sigforms
[formname
]
228 for name
in op_fields
:
230 sig
= getattr(fields
, name
.upper())
232 sig
= getattr(fields
, name
)
234 if name
in ['BF', 'BFA']:
235 self
.namespace
[name
] = val
237 self
.namespace
[name
] = SelectableInt(val
, sig
.width
)
239 self
.namespace
['XER'] = self
.spr
['XER']
240 self
.namespace
['CA'] = self
.spr
['XER'][XER_bits
['CA']].value
242 def handle_carry_(self
, inputs
, outputs
):
243 inv_a
= yield self
.dec2
.e
.invert_a
245 inputs
[0] = ~inputs
[0]
246 assert len(outputs
) >= 1
248 gts
= [(x
> output
) == SelectableInt(1, 1) for x
in inputs
]
254 self
.spr
['XER'][XER_bits
['CA']] = cy
258 gts
= [(x
[32:64] > output
[32:64]) == SelectableInt(1, 1)
260 cy32
= 1 if any(gts
) else 0
261 self
.spr
['XER'][XER_bits
['CA32']] = cy32
264 def handle_comparison(self
, outputs
):
266 out
= exts(out
.value
, out
.bits
)
267 zero
= SelectableInt(out
== 0, 1)
268 positive
= SelectableInt(out
> 0, 1)
269 negative
= SelectableInt(out
< 0, 1)
270 SO
= SelectableInt(0, 1)
271 cr_field
= selectconcat(negative
, positive
, zero
, SO
)
272 self
.crl
[0].eq(cr_field
)
274 def set_pc(self
, pc_val
):
275 self
.namespace
['NIA'] = SelectableInt(pc_val
, 64)
276 self
.pc
.update(self
.namespace
)
279 def call(self
, name
):
280 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
281 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
282 info
= self
.instrs
[name
]
283 yield from self
.prep_namespace(info
.form
, info
.op_fields
)
285 # preserve order of register names
286 input_names
= create_args(list(info
.read_regs
) + list(info
.uninit_regs
))
289 # main registers (RT, RA ...)
291 for name
in input_names
:
292 regnum
= yield getattr(self
.decoder
, name
)
294 self
.namespace
[regname
] = regnum
295 print('reading reg %d' % regnum
)
296 inputs
.append(self
.gpr(regnum
))
298 # "special" registers
299 for special
in info
.special_regs
:
300 if special
in special_sprs
:
301 inputs
.append(self
.spr
[special
])
303 inputs
.append(self
.namespace
[special
])
306 results
= info
.func(self
, *inputs
)
309 rc_en
= yield self
.dec2
.e
.rc
.data
311 self
.handle_comparison(results
)
312 carry_en
= yield self
.dec2
.e
.output_carry
313 yield from self
.handle_carry_(inputs
, results
)
315 # any modified return results?
317 output_names
= create_args(info
.write_regs
)
318 for name
, output
in zip(output_names
, results
):
319 if isinstance(output
, int):
320 output
= SelectableInt(output
, 256)
321 if name
in info
.special_regs
:
322 print('writing special %s' % name
, output
)
323 if name
in special_sprs
:
324 self
.spr
[name
] = output
326 self
.namespace
[name
].eq(output
)
328 regnum
= yield getattr(self
.decoder
, name
)
329 print('writing reg %d %s' % (regnum
, str(output
)))
331 output
= SelectableInt(output
.value
, 64)
332 self
.gpr
[regnum
] = output
334 # update program counter
335 self
.pc
.update(self
.namespace
)
339 """ Decorator factory. """
340 def variable_injector(func
):
342 def decorator(*args
, **kwargs
):
344 func_globals
= func
.__globals
__ # Python 2.6+
345 except AttributeError:
346 func_globals
= func
.func_globals
# Earlier versions.
348 context
= args
[0].namespace
349 saved_values
= func_globals
.copy() # Shallow copy of dict.
350 func_globals
.update(context
)
351 result
= func(*args
, **kwargs
)
352 args
[0].namespace
= func_globals
353 #exec (func.__code__, func_globals)
356 # func_globals = saved_values # Undo changes.
362 return variable_injector