736f7bb59ced1c88aef02586f2a9535b33209323
1 from functools
import wraps
2 from soc
.decoder
.orderedset
import OrderedSet
3 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
5 from collections
import namedtuple
8 instruction_info
= namedtuple('instruction_info',
9 'func read_regs uninit_regs write_regs ' + \
10 'special_regs op_fields form asmregs')
20 def create_args(reglist
, extra
=None):
32 def __init__(self
, bytes_per_word
=8):
34 self
.bytes_per_word
= bytes_per_word
35 self
.word_log2
= math
.ceil(math
.log2(bytes_per_word
))
37 def _get_shifter_mask(self
, width
, remainder
):
38 shifter
= ((self
.bytes_per_word
- width
) - remainder
) * \
40 mask
= (1 << (width
* 8)) - 1
43 # TODO: Implement ld/st of lesser width
44 def ld(self
, address
, width
=8):
45 remainder
= address
& (self
.bytes_per_word
- 1)
46 address
= address
>> self
.word_log2
47 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
48 if address
in self
.mem
:
49 val
= self
.mem
[address
]
53 if width
!= self
.bytes_per_word
:
54 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
55 val
= val
& (mask
<< shifter
)
57 print("Read {:x} from addr {:x}".format(val
, address
))
60 def st(self
, address
, value
, width
=8):
61 remainder
= address
& (self
.bytes_per_word
- 1)
62 address
= address
>> self
.word_log2
63 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
64 print("Writing {:x} to addr {:x}".format(value
, address
))
65 if width
!= self
.bytes_per_word
:
66 if address
in self
.mem
:
67 val
= self
.mem
[address
]
70 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
71 val
&= ~
(mask
<< shifter
)
72 val |
= value
<< shifter
73 self
.mem
[address
] = val
75 self
.mem
[address
] = value
77 def __call__(self
, addr
, sz
):
78 val
= self
.ld(addr
.value
, sz
)
79 print ("memread", addr
, sz
, val
)
80 return SelectableInt(val
, sz
*8)
82 def memassign(self
, addr
, sz
, val
):
83 print ("memassign", addr
, sz
, val
)
84 self
.st(addr
.value
, val
.value
, sz
)
88 def __init__(self
, decoder
, regfile
):
92 self
[i
] = SelectableInt(regfile
[i
], 64)
94 def __call__(self
, ridx
):
97 def set_form(self
, form
):
100 def getz(self
, rnum
):
101 #rnum = rnum.value # only SelectableInt allowed
102 print("GPR getzero", rnum
)
104 return SelectableInt(0, 64)
107 def _get_regnum(self
, attr
):
108 getform
= self
.sd
.sigforms
[self
.form
]
109 rnum
= getattr(getform
, attr
)
112 def ___getitem__(self
, attr
):
113 print("GPR getitem", attr
)
114 rnum
= self
._get
_regnum
(attr
)
115 return self
.regfile
[rnum
]
118 for i
in range(0, len(self
), 8):
121 s
.append("%08x" % self
[i
+j
].value
)
123 print("reg", "%2d" % i
, s
)
126 def __init__(self
, pc_init
=0):
127 self
.CIA
= SelectableInt(pc_init
, 64)
128 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
130 def update(self
, namespace
):
131 self
.CIA
= namespace
['NIA'].narrow(64)
132 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
133 namespace
['CIA'] = self
.CIA
134 namespace
['NIA'] = self
.NIA
138 def __init__(self
, dec2
):
142 def __getitem__(self
, key
):
143 # if key in special_sprs get the special spr, otherwise return key
144 if isinstance(key
, SelectableInt
):
146 key
= special_sprs
.get(key
, key
)
148 return dict.__getitem
__(self
, key
)
150 import pdb
; pdb
.set_trace()
151 return SelectableInt(0, 64)
153 def __setitem__(self
, key
, value
):
154 if isinstance(key
, SelectableInt
):
156 key
= special_sprs
.get(key
, key
)
157 dict.__setitem
__(self
, key
, value
)
159 def __call__(self
, ridx
):
165 # decoder2 - an instance of power_decoder2
166 # regfile - a list of initial values for the registers
167 def __init__(self
, decoder2
, regfile
):
168 self
.gpr
= GPR(decoder2
, regfile
)
171 self
.spr
= SPR(decoder2
)
173 # FPR (same as GPR except for FP nums)
174 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
175 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
176 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
177 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
178 # 2.3.2 LR (actually SPR #8)
179 # 2.3.3 CTR (actually SPR #9)
180 # 2.3.4 TAR (actually SPR #815)
181 # 3.2.2 p45 XER (actually SPR #0)
182 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
184 # create CR then allow portions of it to be "selectable" (below)
185 self
._cr
= SelectableInt(0, 64) # underlying reg
186 self
.cr
= FieldSelectableInt(self
._cr
, list(range(32,64)))
188 # "undefined", just set to variable-bit-width int (use exts "max")
189 self
.undefined
= SelectableInt(0, 256) # TODO, not hard-code 256!
191 self
.namespace
= {'GPR': self
.gpr
,
194 'memassign': self
.memassign
,
198 'undefined': self
.undefined
,
199 'mode_is_64bit': True,
202 # field-selectable versions of Condition Register TODO check bitranges?
205 bits
= tuple(range((7-i
)*4, (8-i
)*4))# errr... maybe?
206 _cr
= FieldSelectableInt(self
.cr
, bits
)
208 self
.namespace
["CR%d" % i
] = _cr
210 self
.decoder
= decoder2
212 def memassign(self
, ea
, sz
, val
):
213 self
.mem
.memassign(ea
, sz
, val
)
215 def prep_namespace(self
, formname
, op_fields
):
216 # TODO: get field names from form in decoder*1* (not decoder2)
217 # decoder2 is hand-created, and decoder1.sigform is auto-generated
219 # then "yield" fields only from op_fields rather than hard-coded
221 fields
= self
.decoder
.sigforms
[formname
]
222 for name
in op_fields
:
224 sig
= getattr(fields
, name
.upper())
226 sig
= getattr(fields
, name
)
228 self
.namespace
[name
] = SelectableInt(val
, sig
.width
)
230 def call(self
, name
):
231 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
232 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
233 info
= self
.instrs
[name
]
234 yield from self
.prep_namespace(info
.form
, info
.op_fields
)
236 # preserve order of register names
237 input_names
= create_args(list(info
.read_regs
) + list(info
.uninit_regs
))
240 # main registers (RT, RA ...)
242 for name
in input_names
:
243 regnum
= yield getattr(self
.decoder
, name
)
245 self
.namespace
[regname
] = regnum
246 print('reading reg %d' % regnum
)
247 inputs
.append(self
.gpr(regnum
))
249 # "special" registers
250 for special
in info
.special_regs
:
251 if special
in special_sprs
:
252 inputs
.append(self
.spr
[special
])
254 inputs
.append(self
.namespace
[special
])
257 results
= info
.func(self
, *inputs
)
260 # any modified return results?
262 output_names
= create_args(info
.write_regs
)
263 for name
, output
in zip(output_names
, results
):
264 if name
in info
.special_regs
:
265 print('writing special %s' % name
, output
)
266 if name
in special_sprs
:
267 self
.spr
[name
] = output
269 self
.namespace
[name
].eq(output
)
271 regnum
= yield getattr(self
.decoder
, name
)
272 print('writing reg %d' % regnum
)
274 output
= SelectableInt(output
.value
, 64)
275 self
.gpr
[regnum
] = output
277 # update program counter
278 self
.pc
.update(self
.namespace
)
282 """ Decorator factory. """
283 def variable_injector(func
):
285 def decorator(*args
, **kwargs
):
287 func_globals
= func
.__globals
__ # Python 2.6+
288 except AttributeError:
289 func_globals
= func
.func_globals
# Earlier versions.
291 context
= args
[0].namespace
292 saved_values
= func_globals
.copy() # Shallow copy of dict.
293 func_globals
.update(context
)
294 result
= func(*args
, **kwargs
)
295 args
[0].namespace
= func_globals
296 #exec (func.__code__, func_globals)
299 # func_globals = saved_values # Undo changes.
305 return variable_injector