83f07be0ae231b3dba2b58ca0a425f9e5fb995c0
1 from functools
import wraps
2 from soc
.decoder
.orderedset
import OrderedSet
3 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
5 from soc
.decoder
.power_enums
import spr_dict
, XER_bits
6 from soc
.decoder
.helpers
import exts
7 from collections
import namedtuple
10 instruction_info
= namedtuple('instruction_info',
11 'func read_regs uninit_regs write_regs ' + \
12 'special_regs op_fields form asmregs')
22 def create_args(reglist
, extra
=None):
34 def __init__(self
, bytes_per_word
=8, initial_mem
=None):
36 self
.bytes_per_word
= bytes_per_word
37 self
.word_log2
= math
.ceil(math
.log2(bytes_per_word
))
40 print ("Sim-Mem", initial_mem
, self
.bytes_per_word
)
41 for addr
, (val
, width
) in initial_mem
.items():
42 self
.st(addr
, val
, width
)
44 def _get_shifter_mask(self
, wid
, remainder
):
45 shifter
= ((self
.bytes_per_word
- wid
) - remainder
) * \
47 mask
= (1 << (wid
* 8)) - 1
48 print ("width,rem,shift,mask", wid
, remainder
, hex(shifter
), hex(mask
))
51 # TODO: Implement ld/st of lesser width
52 def ld(self
, address
, width
=8):
53 print("ld from addr 0x{:x} width {:d}".format(address
, width
))
54 remainder
= address
& (self
.bytes_per_word
- 1)
55 address
= address
>> self
.word_log2
56 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
57 if address
in self
.mem
:
58 val
= self
.mem
[address
]
61 print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address
, remainder
, val
))
63 if width
!= self
.bytes_per_word
:
64 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
65 print ("masking", hex(val
), hex(mask
<<shifter
), shifter
)
66 val
= val
& (mask
<< shifter
)
68 print("Read 0x{:x} from addr 0x{:x}".format(val
, address
))
71 def st(self
, addr
, v
, width
=8):
72 remainder
= addr
& (self
.bytes_per_word
- 1)
73 addr
= addr
>> self
.word_log2
74 print("Writing 0x{:x} to addr 0x{:x}/{:x}".format(v
, addr
, remainder
))
75 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
76 if width
!= self
.bytes_per_word
:
81 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
82 val
&= ~
(mask
<< shifter
)
87 print("mem @ 0x{:x}: 0x{:x}".format(addr
, self
.mem
[addr
]))
89 def __call__(self
, addr
, sz
):
90 val
= self
.ld(addr
.value
, sz
)
91 print ("memread", addr
, sz
, val
)
92 return SelectableInt(val
, sz
*8)
94 def memassign(self
, addr
, sz
, val
):
95 print ("memassign", addr
, sz
, val
)
96 self
.st(addr
.value
, val
.value
, sz
)
100 def __init__(self
, decoder
, regfile
):
104 self
[i
] = SelectableInt(regfile
[i
], 64)
106 def __call__(self
, ridx
):
109 def set_form(self
, form
):
112 def getz(self
, rnum
):
113 #rnum = rnum.value # only SelectableInt allowed
114 print("GPR getzero", rnum
)
116 return SelectableInt(0, 64)
119 def _get_regnum(self
, attr
):
120 getform
= self
.sd
.sigforms
[self
.form
]
121 rnum
= getattr(getform
, attr
)
124 def ___getitem__(self
, attr
):
125 print("GPR getitem", attr
)
126 rnum
= self
._get
_regnum
(attr
)
127 return self
.regfile
[rnum
]
130 for i
in range(0, len(self
), 8):
133 s
.append("%08x" % self
[i
+j
].value
)
135 print("reg", "%2d" % i
, s
)
138 def __init__(self
, pc_init
=0):
139 self
.CIA
= SelectableInt(pc_init
, 64)
140 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
142 def update(self
, namespace
):
143 self
.CIA
= namespace
['NIA'].narrow(64)
144 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
145 namespace
['CIA'] = self
.CIA
146 namespace
['NIA'] = self
.NIA
150 def __init__(self
, dec2
, initial_sprs
={}):
153 self
.update(initial_sprs
)
155 def __getitem__(self
, key
):
156 # if key in special_sprs get the special spr, otherwise return key
157 if isinstance(key
, SelectableInt
):
159 key
= special_sprs
.get(key
, key
)
161 return dict.__getitem
__(self
, key
)
164 dict.__setitem
__(self
, key
, SelectableInt(0, info
.length
))
165 return dict.__getitem
__(self
, key
)
167 def __setitem__(self
, key
, value
):
168 if isinstance(key
, SelectableInt
):
170 key
= special_sprs
.get(key
, key
)
171 dict.__setitem
__(self
, key
, value
)
173 def __call__(self
, ridx
):
179 # decoder2 - an instance of power_decoder2
180 # regfile - a list of initial values for the registers
181 def __init__(self
, decoder2
, regfile
, initial_sprs
=None, initial_cr
=0,
182 initial_mem
=None, initial_msr
=0):
183 if initial_sprs
is None:
185 if initial_mem
is None:
187 self
.gpr
= GPR(decoder2
, regfile
)
188 self
.mem
= Mem(initial_mem
=initial_mem
)
190 self
.spr
= SPR(decoder2
, initial_sprs
)
191 self
.msr
= SelectableInt(initial_msr
, 64) # underlying reg
193 # FPR (same as GPR except for FP nums)
194 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
195 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
196 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
197 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
199 # 2.3.2 LR (actually SPR #8) -- Done
200 # 2.3.3 CTR (actually SPR #9) -- Done
201 # 2.3.4 TAR (actually SPR #815)
202 # 3.2.2 p45 XER (actually SPR #1) -- Done
203 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
205 # create CR then allow portions of it to be "selectable" (below)
206 self
._cr
= SelectableInt(initial_cr
, 64) # underlying reg
207 self
.cr
= FieldSelectableInt(self
._cr
, list(range(32,64)))
209 # "undefined", just set to variable-bit-width int (use exts "max")
210 self
.undefined
= SelectableInt(0, 256) # TODO, not hard-code 256!
212 self
.namespace
= {'GPR': self
.gpr
,
215 'memassign': self
.memassign
,
220 'undefined': self
.undefined
,
221 'mode_is_64bit': True,
225 # field-selectable versions of Condition Register TODO check bitranges?
228 bits
= tuple(range(i
*4, (i
+1)*4))# errr... maybe?
229 _cr
= FieldSelectableInt(self
.cr
, bits
)
231 self
.namespace
["CR%d" % i
] = _cr
233 self
.decoder
= decoder2
.dec
236 def TRAP(self
, trap_addr
=0x700):
238 # store PC in SRR0, set PC to 0x700
239 # store MSR in SRR1, set MSR to um errr something
241 def memassign(self
, ea
, sz
, val
):
242 self
.mem
.memassign(ea
, sz
, val
)
244 def prep_namespace(self
, formname
, op_fields
):
245 # TODO: get field names from form in decoder*1* (not decoder2)
246 # decoder2 is hand-created, and decoder1.sigform is auto-generated
248 # then "yield" fields only from op_fields rather than hard-coded
250 fields
= self
.decoder
.sigforms
[formname
]
251 for name
in op_fields
:
253 sig
= getattr(fields
, name
.upper())
255 sig
= getattr(fields
, name
)
257 if name
in ['BF', 'BFA']:
258 self
.namespace
[name
] = val
260 self
.namespace
[name
] = SelectableInt(val
, sig
.width
)
262 self
.namespace
['XER'] = self
.spr
['XER']
263 self
.namespace
['CA'] = self
.spr
['XER'][XER_bits
['CA']].value
264 self
.namespace
['CA32'] = self
.spr
['XER'][XER_bits
['CA32']].value
266 def handle_carry_(self
, inputs
, outputs
):
267 inv_a
= yield self
.dec2
.e
.invert_a
269 inputs
[0] = ~inputs
[0]
271 imm_ok
= yield self
.dec2
.e
.imm_data
.ok
273 imm
= yield self
.dec2
.e
.imm_data
.data
274 inputs
.append(SelectableInt(imm
, 64))
275 assert len(outputs
) >= 1
277 gts
= [(x
> output
) for x
in inputs
]
279 cy
= 1 if any(gts
) else 0
280 self
.spr
['XER'][XER_bits
['CA']] = cy
282 print ("inputs", inputs
)
284 gts
= [(x
[32:64] > output
[32:64]) == SelectableInt(1, 1)
286 cy32
= 1 if any(gts
) else 0
287 self
.spr
['XER'][XER_bits
['CA32']] = cy32
289 def handle_overflow(self
, inputs
, outputs
):
290 inv_a
= yield self
.dec2
.e
.invert_a
292 inputs
[0] = ~inputs
[0]
294 imm_ok
= yield self
.dec2
.e
.imm_data
.ok
296 imm
= yield self
.dec2
.e
.imm_data
.data
297 inputs
.append(SelectableInt(imm
, 64))
298 assert len(outputs
) >= 1
301 input_sgn
= [exts(x
.value
, x
.bits
) < 0 for x
in inputs
]
302 output_sgn
= exts(output
.value
, output
.bits
) < 0
303 ov
= 1 if input_sgn
[0] == input_sgn
[1] and \
304 output_sgn
!= input_sgn
[0] else 0
306 self
.spr
['XER'][XER_bits
['OV']] = ov
307 so
= self
.spr
['XER'][XER_bits
['SO']]
309 self
.spr
['XER'][XER_bits
['SO']] = so
313 def handle_comparison(self
, outputs
):
315 out
= exts(out
.value
, out
.bits
)
316 zero
= SelectableInt(out
== 0, 1)
317 positive
= SelectableInt(out
> 0, 1)
318 negative
= SelectableInt(out
< 0, 1)
319 SO
= self
.spr
['XER'][XER_bits
['SO']]
320 cr_field
= selectconcat(negative
, positive
, zero
, SO
)
321 self
.crl
[0].eq(cr_field
)
323 def set_pc(self
, pc_val
):
324 self
.namespace
['NIA'] = SelectableInt(pc_val
, 64)
325 self
.pc
.update(self
.namespace
)
328 def call(self
, name
):
329 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
330 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
331 info
= self
.instrs
[name
]
332 yield from self
.prep_namespace(info
.form
, info
.op_fields
)
334 # preserve order of register names
335 input_names
= create_args(list(info
.read_regs
) + list(info
.uninit_regs
))
338 # main registers (RT, RA ...)
340 for name
in input_names
:
341 regnum
= yield getattr(self
.decoder
, name
)
343 self
.namespace
[regname
] = regnum
344 print('reading reg %d' % regnum
)
345 inputs
.append(self
.gpr(regnum
))
347 # "special" registers
348 for special
in info
.special_regs
:
349 if special
in special_sprs
:
350 inputs
.append(self
.spr
[special
])
352 inputs
.append(self
.namespace
[special
])
355 results
= info
.func(self
, *inputs
)
358 carry_en
= yield self
.dec2
.e
.output_carry
360 yield from self
.handle_carry_(inputs
, results
)
361 ov_en
= yield self
.dec2
.e
.oe
363 yield from self
.handle_overflow(inputs
, results
)
364 rc_en
= yield self
.dec2
.e
.rc
.data
366 self
.handle_comparison(results
)
368 # any modified return results?
370 output_names
= create_args(info
.write_regs
)
371 for name
, output
in zip(output_names
, results
):
372 if isinstance(output
, int):
373 output
= SelectableInt(output
, 256)
374 if name
in ['CA', 'CA32']:
376 print ("writing %s to XER" % name
, output
)
377 self
.spr
['XER'][XER_bits
[name
]] = output
.value
379 print ("NOT writing %s to XER" % name
, output
)
380 elif name
in info
.special_regs
:
381 print('writing special %s' % name
, output
, special_sprs
)
382 if name
in special_sprs
:
383 self
.spr
[name
] = output
385 self
.namespace
[name
].eq(output
)
387 regnum
= yield getattr(self
.decoder
, name
)
388 print('writing reg %d %s' % (regnum
, str(output
)))
390 output
= SelectableInt(output
.value
, 64)
391 self
.gpr
[regnum
] = output
393 # update program counter
394 self
.pc
.update(self
.namespace
)
398 """Decorator factory.
400 this decorator will "inject" variables into the function's namespace,
401 from the *dictionary* in self.namespace. it therefore becomes possible
402 to make it look like a whole stack of variables which would otherwise
403 need "self." inserted in front of them (*and* for those variables to be
404 added to the instance) "appear" in the function.
406 "self.namespace['SI']" for example becomes accessible as just "SI" but
407 *only* inside the function, when decorated.
409 def variable_injector(func
):
411 def decorator(*args
, **kwargs
):
413 func_globals
= func
.__globals
__ # Python 2.6+
414 except AttributeError:
415 func_globals
= func
.func_globals
# Earlier versions.
417 context
= args
[0].namespace
# variables to be injected
418 saved_values
= func_globals
.copy() # Shallow copy of dict.
419 func_globals
.update(context
)
420 result
= func(*args
, **kwargs
)
421 args
[0].namespace
= func_globals
422 #exec (func.__code__, func_globals)
425 # func_globals = saved_values # Undo changes.
431 return variable_injector