src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
   7 from nmigen.cli import rtlil
   8
   9 from nmutil.iocontrol import RecordObject
  10 from nmutil.extend import exts
  11
  12 from soc.decoder.power_regspec_map import regspec_decode
  13 from soc.decoder.power_decoder import create_pdecode
  14 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  15                                      CRInSel, CROutSel,
  16                                      LdstLen, In1Sel, In2Sel, In3Sel,
  17                                      OutSel, SPR, RC)
  18
  19 from soc.regfile.regfiles import FastRegs
  20
  21 class DecodeA(Elaboratable):
  22     """DecodeA from instruction
  23
  24     decodes register RA, whether immediate-zero, implicit and
  25     explicit CSRs
  26     """
  27
  28     def __init__(self, dec):
  29         self.dec = dec
  30         self.sel_in = Signal(In1Sel, reset_less=True)
  31         self.insn_in = Signal(32, reset_less=True)
  32         self.reg_out = Data(5, name="reg_a")
  33         self.immz_out = Signal(reset_less=True)
  34         self.spr_out = Data(10, "spr_a")
  35         self.fast_out = Data(3, "fast_a")
  36
  37     def elaborate(self, platform):
  38         m = Module()
  39         comb = m.d.comb
  40
  41         # select Register A field
  42         ra = Signal(5, reset_less=True)
  43         comb += ra.eq(self.dec.RA)
  44         with m.If((self.sel_in == In1Sel.RA) |
  45                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  46                    (ra != Const(0, 5)))):
  47             comb += self.reg_out.data.eq(ra)
  48             comb += self.reg_out.ok.eq(1)
  49
  50         # zero immediate requested
  51         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  52                   (self.reg_out.data == Const(0, 5))):
  53             comb += self.immz_out.eq(1)
  54
  55         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
  56         with m.If(self.sel_in == In1Sel.RS):
  57             comb += self.reg_out.data.eq(self.dec.RS)
  58             comb += self.reg_out.ok.eq(1)
  59
  60         # decode Fast-SPR based on instruction type
  61         op = self.dec.op
  62         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeOut
  63         with m.If(op.internal_op == InternalOp.OP_BC):
  64             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  65                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  66                 comb += self.fast_out.ok.eq(1)
  67         with m.Elif(op.internal_op == InternalOp.OP_BCREG):
  68             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
  69             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
  70             with m.If(xo9 & ~xo5):
  71                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
  72                 comb += self.fast_out.ok.eq(1)
  73
  74         # MFSPR move from SPRs
  75         with m.If(op.internal_op == InternalOp.OP_MFSPR):
  76             # XXX TODO: fast/slow SPR decoding and mapping
  77             comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
  78             comb += self.spr_out.ok.eq(1)
  79
  80         return m
  81
  82
  83 class Data(Record):
  84
  85     def __init__(self, width, name):
  86         name_ok = "%s_ok" % name
  87         layout = ((name, width), (name_ok, 1))
  88         Record.__init__(self, layout)
  89         self.data = getattr(self, name) # convenience
  90         self.ok = getattr(self, name_ok) # convenience
  91         self.data.reset_less = True # grrr
  92         self.reset_less = True # grrr
  93
  94     def ports(self):
  95         return [self.data, self.ok]
  96
  97
  98 class DecodeB(Elaboratable):
  99     """DecodeB from instruction
 100
 101     decodes register RB, different forms of immediate (signed, unsigned),
 102     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 103     by industry-standard convention, "lane 2" is where fully-decoded
 104     immediates are muxed in.
 105     """
 106
 107     def __init__(self, dec):
 108         self.dec = dec
 109         self.sel_in = Signal(In2Sel, reset_less=True)
 110         self.insn_in = Signal(32, reset_less=True)
 111         self.reg_out = Data(5, "reg_b")
 112         self.imm_out = Data(64, "imm_b")
 113         self.fast_out = Data(3, "fast_b")
 114
 115     def elaborate(self, platform):
 116         m = Module()
 117         comb = m.d.comb
 118
 119         # select Register B field
 120         with m.Switch(self.sel_in):
 121             with m.Case(In2Sel.RB):
 122                 comb += self.reg_out.data.eq(self.dec.RB)
 123                 comb += self.reg_out.ok.eq(1)
 124             with m.Case(In2Sel.RS):
 125                 comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot
 126                 comb += self.reg_out.ok.eq(1)
 127             with m.Case(In2Sel.CONST_UI):
 128                 comb += self.imm_out.data.eq(self.dec.UI)
 129                 comb += self.imm_out.ok.eq(1)
 130             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 131                 comb += self.imm_out.data.eq(
 132                     exts(self.dec.SI, 16, 64))
 133                 comb += self.imm_out.ok.eq(1)
 134             with m.Case(In2Sel.CONST_UI_HI):
 135                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 136                 comb += self.imm_out.ok.eq(1)
 137             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 138                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 139                 comb += self.imm_out.data.eq(
 140                     exts(self.dec.SI << 16, 32, 64))
 141                 comb += self.imm_out.ok.eq(1)
 142             with m.Case(In2Sel.CONST_LI):
 143                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 144                 comb += self.imm_out.ok.eq(1)
 145             with m.Case(In2Sel.CONST_BD):
 146                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 147                 comb += self.imm_out.ok.eq(1)
 148             with m.Case(In2Sel.CONST_DS):
 149                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 150                 comb += self.imm_out.ok.eq(1)
 151             with m.Case(In2Sel.CONST_M1):
 152                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 153                 comb += self.imm_out.ok.eq(1)
 154             with m.Case(In2Sel.CONST_SH):
 155                 comb += self.imm_out.data.eq(self.dec.sh)
 156                 comb += self.imm_out.ok.eq(1)
 157             with m.Case(In2Sel.CONST_SH32):
 158                 comb += self.imm_out.data.eq(self.dec.SH32)
 159                 comb += self.imm_out.ok.eq(1)
 160
 161         # decode SPR2 based on instruction type
 162         op = self.dec.op
 163         # BCREG implicitly uses LR or TAR for 2nd reg
 164         # CTR however is already in fast_spr1 *not* 2.
 165         with m.If(op.internal_op == InternalOp.OP_BCREG):
 166             xo9 = self.dec.FormXL.XO[9] # 3.0B p38 top bit of XO
 167             xo5 = self.dec.FormXL.XO[5] # 3.0B p38
 168             with m.If(~xo9):
 169                 comb += self.fast_out.data.eq(FastRegs.LR)
 170                 comb += self.fast_out.ok.eq(1)
 171             with m.Elif(xo5):
 172                 comb += self.fast_out.data.eq(FastRegs.TAR)
 173                 comb += self.fast_out.ok.eq(1)
 174
 175         return m
 176
 177
 178 class DecodeC(Elaboratable):
 179     """DecodeC from instruction
 180
 181     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 182     """
 183
 184     def __init__(self, dec):
 185         self.dec = dec
 186         self.sel_in = Signal(In3Sel, reset_less=True)
 187         self.insn_in = Signal(32, reset_less=True)
 188         self.reg_out = Data(5, "reg_c")
 189
 190     def elaborate(self, platform):
 191         m = Module()
 192         comb = m.d.comb
 193
 194         # select Register C field
 195         with m.Switch(self.sel_in):
 196             with m.Case(In3Sel.RB):
 197                 comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot
 198                 comb += self.reg_out.ok.eq(1)
 199             with m.Case(In3Sel.RS):
 200                 comb += self.reg_out.data.eq(self.dec.RS)
 201                 comb += self.reg_out.ok.eq(1)
 202
 203         return m
 204
 205
 206 class DecodeOut(Elaboratable):
 207     """DecodeOut from instruction
 208
 209     decodes output register RA, RT or SPR
 210     """
 211
 212     def __init__(self, dec):
 213         self.dec = dec
 214         self.sel_in = Signal(OutSel, reset_less=True)
 215         self.insn_in = Signal(32, reset_less=True)
 216         self.reg_out = Data(5, "reg_o")
 217         self.spr_out = Data(10, "spr_o")
 218         self.fast_out = Data(3, "fast_o")
 219
 220     def elaborate(self, platform):
 221         m = Module()
 222         comb = m.d.comb
 223         op = self.dec.op
 224
 225         # select Register out field
 226         with m.Switch(self.sel_in):
 227             with m.Case(OutSel.RT):
 228                 comb += self.reg_out.data.eq(self.dec.RT)
 229                 comb += self.reg_out.ok.eq(1)
 230             with m.Case(OutSel.RA):
 231                 comb += self.reg_out.data.eq(self.dec.RA)
 232                 comb += self.reg_out.ok.eq(1)
 233             with m.Case(OutSel.SPR):
 234                 comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
 235                 comb += self.spr_out.ok.eq(1)
 236                 # TODO MTSPR 1st spr (fast)
 237                 with m.If(op.internal_op == InternalOp.OP_MTSPR):
 238                     pass
 239                     """
 240                     sprn := decode_spr_num(f_in.insn);
 241                     v.ispr1 := fast_spr_num(sprn);
 242                     -- Make slow SPRs single issue
 243                     if is_fast_spr(v.ispr1) = '0' then
 244                         v.decode.sgl_pipe := '1';
 245                         -- send MMU-related SPRs to loadstore1
 246                         case sprn is
 247                         when SPR_DAR | SPR_DSISR | SPR_PID | SPR_PRTBL =>
 248                             v.decode.unit := LDST;
 249                         when others =>
 250                         end case;
 251                     end if;
 252                     """
 253
 254
 255         # BC or BCREG: potential implicit register (CTR) NOTE: same in DecodeA
 256         op = self.dec.op
 257         with m.If((op.internal_op == InternalOp.OP_BC) |
 258                   (op.internal_op == InternalOp.OP_BCREG)):
 259             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
 260                 comb += self.fast_out.data.eq(FastRegs.CTR) # constant: CTR
 261                 comb += self.fast_out.ok.eq(1)
 262
 263         # RFID 1st spr (fast)
 264         with m.If(op.internal_op == InternalOp.OP_RFID):
 265             comb += self.fast_out.data.eq(FastRegs.SRR0) # constant: SRR0
 266             comb += self.fast_out.ok.eq(1)
 267
 268         return m
 269
 270
 271 class DecodeOut2(Elaboratable):
 272     """DecodeOut2 from instruction
 273
 274     decodes output registers
 275     """
 276
 277     def __init__(self, dec):
 278         self.dec = dec
 279         self.sel_in = Signal(OutSel, reset_less=True)
 280         self.lk = Signal(reset_less=True)
 281         self.insn_in = Signal(32, reset_less=True)
 282         self.reg_out = Data(5, "reg_o")
 283         self.fast_out = Data(3, "fast_o")
 284
 285     def elaborate(self, platform):
 286         m = Module()
 287         comb = m.d.comb
 288
 289         # update mode LD/ST uses read-reg A also as an output
 290         with m.If(self.dec.op.upd):
 291             comb += self.reg_out.eq(self.dec.RA)
 292             comb += self.reg_out.ok.eq(1)
 293
 294         # BC or BCREG: potential implicit register (LR) output
 295         op = self.dec.op
 296         with m.If((op.internal_op == InternalOp.OP_BC) |
 297                   (op.internal_op == InternalOp.OP_BCREG)):
 298             with m.If(self.lk): # "link" mode
 299                 comb += self.fast_out.data.eq(FastRegs.LR) # constant: LR
 300                 comb += self.fast_out.ok.eq(1)
 301
 302         # RFID 2nd spr (fast)
 303         with m.If(op.internal_op == InternalOp.OP_RFID):
 304                 comb += self.fast_out.data.eq(FastRegs.SRR1) # constant: SRR1
 305                 comb += self.fast_out.ok.eq(1)
 306
 307         return m
 308
 309
 310 class DecodeRC(Elaboratable):
 311     """DecodeRc from instruction
 312
 313     decodes Record bit Rc
 314     """
 315     def __init__(self, dec):
 316         self.dec = dec
 317         self.sel_in = Signal(RC, reset_less=True)
 318         self.insn_in = Signal(32, reset_less=True)
 319         self.rc_out = Data(1, "rc")
 320
 321     def elaborate(self, platform):
 322         m = Module()
 323         comb = m.d.comb
 324
 325         # select Record bit out field
 326         with m.Switch(self.sel_in):
 327             with m.Case(RC.RC):
 328                 comb += self.rc_out.data.eq(self.dec.Rc)
 329                 comb += self.rc_out.ok.eq(1)
 330             with m.Case(RC.ONE):
 331                 comb += self.rc_out.data.eq(1)
 332                 comb += self.rc_out.ok.eq(1)
 333             with m.Case(RC.NONE):
 334                 comb += self.rc_out.data.eq(0)
 335                 comb += self.rc_out.ok.eq(1)
 336
 337         return m
 338
 339
 340 class DecodeOE(Elaboratable):
 341     """DecodeOE from instruction
 342
 343     decodes OE field: uses RC decode detection which might not be good
 344
 345     -- For now, use "rc" in the decode table to decide whether oe exists.
 346     -- This is not entirely correct architecturally: For mulhd and
 347     -- mulhdu, the OE field is reserved. It remains to be seen what an
 348     -- actual POWER9 does if we set it on those instructions, for now we
 349     -- test that further down when assigning to the multiplier oe input.
 350     """
 351     def __init__(self, dec):
 352         self.dec = dec
 353         self.sel_in = Signal(RC, reset_less=True)
 354         self.insn_in = Signal(32, reset_less=True)
 355         self.oe_out = Data(1, "oe")
 356
 357     def elaborate(self, platform):
 358         m = Module()
 359         comb = m.d.comb
 360
 361         # select OE bit out field
 362         with m.Switch(self.sel_in):
 363             with m.Case(RC.RC):
 364                 comb += self.oe_out.data.eq(self.dec.OE)
 365                 comb += self.oe_out.ok.eq(1)
 366
 367         return m
 368
 369 class DecodeCRIn(Elaboratable):
 370     """Decodes input CR from instruction
 371
 372     CR indices - insn fields - (not the data *in* the CR) require only 3
 373     bits because they refer to CR0-CR7
 374     """
 375
 376     def __init__(self, dec):
 377         self.dec = dec
 378         self.sel_in = Signal(CRInSel, reset_less=True)
 379         self.insn_in = Signal(32, reset_less=True)
 380         self.cr_bitfield = Data(3, "cr_bitfield")
 381         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 382         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 383         self.whole_reg = Signal(reset_less=True)
 384
 385     def elaborate(self, platform):
 386         m = Module()
 387         comb = m.d.comb
 388
 389         comb += self.cr_bitfield.ok.eq(0)
 390         comb += self.cr_bitfield_b.ok.eq(0)
 391         comb += self.whole_reg.eq(0)
 392         with m.Switch(self.sel_in):
 393             with m.Case(CRInSel.NONE):
 394                 pass # No bitfield activated
 395             with m.Case(CRInSel.CR0):
 396                 comb += self.cr_bitfield.data.eq(0)
 397                 comb += self.cr_bitfield.ok.eq(1)
 398             with m.Case(CRInSel.BI):
 399                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 400                 comb += self.cr_bitfield.ok.eq(1)
 401             with m.Case(CRInSel.BFA):
 402                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 403                 comb += self.cr_bitfield.ok.eq(1)
 404             with m.Case(CRInSel.BA_BB):
 405                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 406                 comb += self.cr_bitfield.ok.eq(1)
 407                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 408                 comb += self.cr_bitfield_b.ok.eq(1)
 409                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 410                 comb += self.cr_bitfield_o.ok.eq(1)
 411             with m.Case(CRInSel.BC):
 412                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 413                 comb += self.cr_bitfield.ok.eq(1)
 414             with m.Case(CRInSel.WHOLE_REG):
 415                 comb += self.whole_reg.eq(1)
 416
 417         return m
 418
 419
 420 class DecodeCROut(Elaboratable):
 421     """Decodes input CR from instruction
 422
 423     CR indices - insn fields - (not the data *in* the CR) require only 3
 424     bits because they refer to CR0-CR7
 425     """
 426
 427     def __init__(self, dec):
 428         self.dec = dec
 429         self.rc_in = Signal(reset_less=True)
 430         self.sel_in = Signal(CROutSel, reset_less=True)
 431         self.insn_in = Signal(32, reset_less=True)
 432         self.cr_bitfield = Data(3, "cr_bitfield")
 433         self.whole_reg = Signal(reset_less=True)
 434
 435     def elaborate(self, platform):
 436         m = Module()
 437         comb = m.d.comb
 438
 439         comb += self.cr_bitfield.ok.eq(0)
 440         comb += self.whole_reg.eq(0)
 441         with m.Switch(self.sel_in):
 442             with m.Case(CROutSel.NONE):
 443                 pass # No bitfield activated
 444             with m.Case(CROutSel.CR0):
 445                 comb += self.cr_bitfield.data.eq(0)
 446                 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
 447             with m.Case(CROutSel.BF):
 448                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF[0:-1])
 449                 comb += self.cr_bitfield.ok.eq(1)
 450             with m.Case(CROutSel.BT):
 451                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 452                 comb += self.cr_bitfield.ok.eq(1)
 453             with m.Case(CROutSel.WHOLE_REG):
 454                 comb += self.whole_reg.eq(1)
 455
 456         return m
 457
 458
 459 class XerBits:
 460     def __init__(self):
 461         self.ca = Signal(2, reset_less=True)
 462         self.ov = Signal(2, reset_less=True)
 463         self.so = Signal(reset_less=True)
 464
 465     def ports(self):
 466         return [self.ca, self.ov, self.so]
 467
 468
 469 class Decode2ToExecute1Type(RecordObject):
 470
 471     def __init__(self, name=None):
 472
 473         RecordObject.__init__(self, name=name)
 474
 475         self.valid = Signal(reset_less=True)
 476         self.insn_type = Signal(InternalOp, reset_less=True)
 477         self.fn_unit = Signal(Function, reset_less=True)
 478         self.nia = Signal(64, reset_less=True)
 479         self.write_reg = Data(5, name="rego")
 480         self.write_ea = Data(5, name="ea") # for LD/ST in update mode
 481         self.read_reg1 = Data(5, name="reg1")
 482         self.read_reg2 = Data(5, name="reg2")
 483         self.read_reg3 = Data(5, name="reg3")
 484         self.imm_data = Data(64, name="imm")
 485         self.write_spr = Data(10, name="spro")
 486         self.read_spr1 = Data(10, name="spr1")
 487         self.read_spr2 = Data(10, name="spr2")
 488
 489         self.read_fast1 = Data(3, name="fast1")
 490         self.read_fast2 = Data(3, name="fast2")
 491         self.write_fast1 = Data(3, name="fasto1")
 492         self.write_fast2 = Data(3, name="fasto2")
 493
 494         self.read_cr1 = Data(3, name="cr_in1")
 495         self.read_cr2 = Data(3, name="cr_in2")
 496         self.read_cr3 = Data(3, name="cr_in2")
 497         self.read_cr_whole = Signal(reset_less=True)
 498         self.write_cr = Data(3, name="cr_out")
 499         self.write_cr_whole = Signal(reset_less=True)
 500         self.lk = Signal(reset_less=True)
 501         self.rc = Data(1, "rc")
 502         self.oe = Data(1, "oe")
 503         self.invert_a = Signal(reset_less=True)
 504         self.zero_a = Signal(reset_less=True)
 505         self.invert_out = Signal(reset_less=True)
 506         self.input_carry = Signal(CryIn, reset_less=True)
 507         self.output_carry = Signal(reset_less=True)
 508         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
 509         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
 510         self.is_32bit = Signal(reset_less=True)
 511         self.is_signed = Signal(reset_less=True)
 512         self.insn = Signal(32, reset_less=True)
 513         self.data_len = Signal(4, reset_less=True) # bytes
 514         self.byte_reverse  = Signal(reset_less=True)
 515         self.sign_extend  = Signal(reset_less=True)# do we need this?
 516         self.update  = Signal(reset_less=True) # LD/ST is "update" variant
 517
 518
 519 class PowerDecode2(Elaboratable):
 520
 521     def __init__(self, dec):
 522
 523         self.dec = dec
 524         self.e = Decode2ToExecute1Type()
 525
 526     def ports(self):
 527         return self.dec.ports() + self.e.ports()
 528
 529     def elaborate(self, platform):
 530         m = Module()
 531         comb = m.d.comb
 532
 533         # set up submodule decoders
 534         m.submodules.dec = self.dec
 535         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 536         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 537         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 538         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 539         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 540         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 541         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 542         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 543         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 544
 545         # copy instruction through...
 546         for i in [self.e.insn, dec_a.insn_in, dec_b.insn_in,
 547                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 548                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 549             comb += i.eq(self.dec.opcode_in)
 550
 551         # ...and subdecoders' input fields
 552         comb += dec_a.sel_in.eq(self.dec.op.in1_sel)
 553         comb += dec_b.sel_in.eq(self.dec.op.in2_sel)
 554         comb += dec_c.sel_in.eq(self.dec.op.in3_sel)
 555         comb += dec_o.sel_in.eq(self.dec.op.out_sel)
 556         comb += dec_o2.sel_in.eq(self.dec.op.out_sel)
 557         comb += dec_o2.lk.eq(self.e.lk)
 558         comb += dec_rc.sel_in.eq(self.dec.op.rc_sel)
 559         comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel
 560         comb += dec_cr_in.sel_in.eq(self.dec.op.cr_in)
 561         comb += dec_cr_out.sel_in.eq(self.dec.op.cr_out)
 562         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 563
 564         # decode LD/ST length
 565         with m.Switch(self.dec.op.ldst_len):
 566             with m.Case(LdstLen.is1B):
 567                 comb += self.e.data_len.eq(1)
 568             with m.Case(LdstLen.is2B):
 569                 comb += self.e.data_len.eq(2)
 570             with m.Case(LdstLen.is4B):
 571                 comb += self.e.data_len.eq(4)
 572             with m.Case(LdstLen.is8B):
 573                 comb += self.e.data_len.eq(8)
 574
 575         comb += self.e.nia.eq(0)    # XXX TODO
 576         fu = self.dec.op.function_unit
 577         itype = Mux(fu == Function.NONE,
 578                     InternalOp.OP_ILLEGAL,
 579                     self.dec.op.internal_op)
 580         comb += self.e.insn_type.eq(itype)
 581         comb += self.e.fn_unit.eq(fu)
 582
 583         # registers a, b, c and out and out2 (LD/ST EA)
 584         comb += self.e.read_reg1.eq(dec_a.reg_out)
 585         comb += self.e.read_reg2.eq(dec_b.reg_out)
 586         comb += self.e.read_reg3.eq(dec_c.reg_out)
 587         comb += self.e.write_reg.eq(dec_o.reg_out)
 588         comb += self.e.write_ea.eq(dec_o2.reg_out)
 589         comb += self.e.imm_data.eq(dec_b.imm_out) # immediate in RB (usually)
 590         comb += self.e.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 591
 592         # rc and oe out
 593         comb += self.e.rc.eq(dec_rc.rc_out)
 594         comb += self.e.oe.eq(dec_oe.oe_out)
 595
 596         # SPRs out
 597         comb += self.e.read_spr1.eq(dec_a.spr_out)
 598         comb += self.e.write_spr.eq(dec_o.spr_out)
 599
 600         # Fast regs out
 601         comb += self.e.read_fast1.eq(dec_a.fast_out)
 602         comb += self.e.read_fast2.eq(dec_b.fast_out)
 603         comb += self.e.write_fast1.eq(dec_o.fast_out)
 604         comb += self.e.write_fast2.eq(dec_o2.fast_out)
 605
 606         comb += self.e.read_cr1.eq(dec_cr_in.cr_bitfield)
 607         comb += self.e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 608         comb += self.e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 609         comb += self.e.read_cr_whole.eq(dec_cr_in.whole_reg)
 610
 611         comb += self.e.write_cr.eq(dec_cr_out.cr_bitfield)
 612         comb += self.e.write_cr_whole.eq(dec_cr_out.whole_reg)
 613
 614         # decoded/selected instruction flags
 615         comb += self.e.invert_a.eq(self.dec.op.inv_a)
 616         comb += self.e.invert_out.eq(self.dec.op.inv_out)
 617         comb += self.e.input_carry.eq(self.dec.op.cry_in)   # carry comes in
 618         comb += self.e.output_carry.eq(self.dec.op.cry_out) # carry goes out
 619         comb += self.e.is_32bit.eq(self.dec.op.is_32b)
 620         comb += self.e.is_signed.eq(self.dec.op.sgn)
 621         with m.If(self.dec.op.lk):
 622             comb += self.e.lk.eq(self.dec.LK) # XXX TODO: accessor
 623
 624         comb += self.e.byte_reverse.eq(self.dec.op.br)
 625         comb += self.e.sign_extend.eq(self.dec.op.sgn_ext)
 626         comb += self.e.update.eq(self.dec.op.upd) # LD/ST "update" mode.
 627
 628
 629         # These should be removed eventually
 630         comb += self.e.input_cr.eq(self.dec.op.cr_in)   # condition reg comes in
 631         comb += self.e.output_cr.eq(self.dec.op.cr_out) # condition reg goes in
 632
 633
 634         return m
 635
 636     def regspecmap(self, regfile, regname):
 637         """regspecmap: provides PowerDecode2 with an encoding relationship
 638         to Function Unit port regfiles (read-enable, read regnum, write regnum)
 639         regfile and regname arguments are fields 1 and 2 from a given regspec.
 640         """
 641         return regspec_decode(self.e, regfile, regname)
 642
 643     def rdflags(self, cu):
 644         rdl = []
 645         for idx in range(cu.n_src):
 646             regfile, regname, _ = cu.get_in_spec(idx)
 647             rdflag, read, write = self.regspecmap(regfile, regname)
 648             rdl.append(rdflag)
 649         print ("rdflags", rdl)
 650         return Cat(*rdl)
 651
 652
 653 if __name__ == '__main__':
 654     pdecode = create_pdecode()
 655     dec2 = PowerDecode2(pdecode)
 656     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 657     with open("dec2.il", "w") as f:
 658         f.write(vl)
 659