src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
   7 from nmigen.cli import rtlil
   8
   9 from nmutil.iocontrol import RecordObject
  10 from nmutil.extend import exts
  11
  12 from soc.decoder.power_decoder import create_pdecode
  13 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
  14                                      CRInSel, CROutSel,
  15                                      LdstLen, In1Sel, In2Sel, In3Sel,
  16                                      OutSel, SPR, RC)
  17
  18
  19 class DecodeA(Elaboratable):
  20     """DecodeA from instruction
  21
  22     decodes register RA, whether immediate-zero, implicit and
  23     explicit CSRs
  24     """
  25
  26     def __init__(self, dec):
  27         self.dec = dec
  28         self.sel_in = Signal(In1Sel, reset_less=True)
  29         self.insn_in = Signal(32, reset_less=True)
  30         self.reg_out = Data(5, name="reg_a")
  31         self.immz_out = Signal(reset_less=True)
  32         self.spr_out = Data(10, "spr_a")
  33
  34     def elaborate(self, platform):
  35         m = Module()
  36         comb = m.d.comb
  37
  38         # select Register A field
  39         ra = Signal(5, reset_less=True)
  40         comb += ra.eq(self.dec.RA)
  41         with m.If((self.sel_in == In1Sel.RA) |
  42                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  43                    (ra != Const(0, 5)))):
  44             comb += self.reg_out.data.eq(ra)
  45             comb += self.reg_out.ok.eq(1)
  46
  47         # zero immediate requested
  48         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
  49                   (self.reg_out.data == Const(0, 5))):
  50             comb += self.immz_out.eq(1)
  51
  52         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
  53         with m.If(self.sel_in == In1Sel.RS):
  54             comb += self.reg_out.data.eq(self.dec.RS)
  55             comb += self.reg_out.ok.eq(1)
  56
  57         # decode SPR1 based on instruction type
  58         op = self.dec.op
  59         # BC or BCREG: potential implicit register (CTR)
  60         with m.If((op.internal_op == InternalOp.OP_BC) |
  61                   (op.internal_op == InternalOp.OP_BCREG)):
  62             with m.If(~self.dec.BO[2]): # 3.0B p38 BO2=0, use CTR reg
  63                 comb += self.spr_out.data.eq(SPR.CTR) # constant: CTR
  64                 comb += self.spr_out.ok.eq(1)
  65         # MFSPR or MTSPR: move-from / move-to SPRs
  66         with m.If((op.internal_op == InternalOp.OP_MFSPR) |
  67                   (op.internal_op == InternalOp.OP_MTSPR)):
  68             comb += self.spr_out.data.eq(self.dec.SPR) # SPR field, XFX
  69             comb += self.spr_out.ok.eq(1)
  70
  71         return m
  72
  73
  74 class Data(Record):
  75
  76     def __init__(self, width, name):
  77         name_ok = "%s_ok" % name
  78         layout = ((name, width), (name_ok, 1))
  79         Record.__init__(self, layout)
  80         self.data = getattr(self, name) # convenience
  81         self.ok = getattr(self, name_ok) # convenience
  82         self.data.reset_less = True # grrr
  83         self.reset_less = True # grrr
  84
  85     def ports(self):
  86         return [self.data, self.ok]
  87
  88
  89 class DecodeB(Elaboratable):
  90     """DecodeB from instruction
  91
  92     decodes register RB, different forms of immediate (signed, unsigned),
  93     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
  94     by industry-standard convention, "lane 2" is where fully-decoded
  95     immediates are muxed in.
  96     """
  97
  98     def __init__(self, dec):
  99         self.dec = dec
 100         self.sel_in = Signal(In2Sel, reset_less=True)
 101         self.insn_in = Signal(32, reset_less=True)
 102         self.reg_out = Data(5, "reg_b")
 103         self.imm_out = Data(64, "imm_b")
 104         self.spr_out = Data(10, "spr_b")
 105
 106     def elaborate(self, platform):
 107         m = Module()
 108         comb = m.d.comb
 109
 110         # select Register B field
 111         with m.Switch(self.sel_in):
 112             with m.Case(In2Sel.RB):
 113                 comb += self.reg_out.data.eq(self.dec.RB)
 114                 comb += self.reg_out.ok.eq(1)
 115             with m.Case(In2Sel.RS):
 116                 comb += self.reg_out.data.eq(self.dec.RS) # for M-Form shiftrot
 117                 comb += self.reg_out.ok.eq(1)
 118             with m.Case(In2Sel.CONST_UI):
 119                 comb += self.imm_out.data.eq(self.dec.UI)
 120                 comb += self.imm_out.ok.eq(1)
 121             with m.Case(In2Sel.CONST_SI): # TODO: sign-extend here?
 122                 comb += self.imm_out.data.eq(
 123                     exts(self.dec.SI, 16, 64))
 124                 comb += self.imm_out.ok.eq(1)
 125             with m.Case(In2Sel.CONST_UI_HI):
 126                 comb += self.imm_out.data.eq(self.dec.UI<<16)
 127                 comb += self.imm_out.ok.eq(1)
 128             with m.Case(In2Sel.CONST_SI_HI): # TODO: sign-extend here?
 129                 comb += self.imm_out.data.eq(self.dec.SI<<16)
 130                 comb += self.imm_out.data.eq(
 131                     exts(self.dec.SI << 16, 32, 64))
 132                 comb += self.imm_out.ok.eq(1)
 133             with m.Case(In2Sel.CONST_LI):
 134                 comb += self.imm_out.data.eq(self.dec.LI<<2)
 135                 comb += self.imm_out.ok.eq(1)
 136             with m.Case(In2Sel.CONST_BD):
 137                 comb += self.imm_out.data.eq(self.dec.BD<<2)
 138                 comb += self.imm_out.ok.eq(1)
 139             with m.Case(In2Sel.CONST_DS):
 140                 comb += self.imm_out.data.eq(self.dec.DS<<2)
 141                 comb += self.imm_out.ok.eq(1)
 142             with m.Case(In2Sel.CONST_M1):
 143                 comb += self.imm_out.data.eq(~Const(0, 64)) # all 1s
 144                 comb += self.imm_out.ok.eq(1)
 145             with m.Case(In2Sel.CONST_SH):
 146                 comb += self.imm_out.data.eq(self.dec.sh)
 147                 comb += self.imm_out.ok.eq(1)
 148             with m.Case(In2Sel.CONST_SH32):
 149                 comb += self.imm_out.data.eq(self.dec.SH32)
 150                 comb += self.imm_out.ok.eq(1)
 151
 152         # decode SPR2 based on instruction type
 153         op = self.dec.op
 154         # BCREG implicitly uses CTR or LR for 2nd reg
 155         with m.If(op.internal_op == InternalOp.OP_BCREG):
 156             with m.If(self.dec.FormXL.XO[9]): # 3.0B p38 top bit of XO
 157                 comb += self.spr_out.data.eq(SPR.CTR)
 158             with m.Else():
 159                 comb += self.spr_out.data.eq(SPR.LR)
 160             comb += self.spr_out.ok.eq(1)
 161
 162         return m
 163
 164
 165 class DecodeC(Elaboratable):
 166     """DecodeC from instruction
 167
 168     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 169     """
 170
 171     def __init__(self, dec):
 172         self.dec = dec
 173         self.sel_in = Signal(In3Sel, reset_less=True)
 174         self.insn_in = Signal(32, reset_less=True)
 175         self.reg_out = Data(5, "reg_c")
 176
 177     def elaborate(self, platform):
 178         m = Module()
 179         comb = m.d.comb
 180
 181         # select Register C field
 182         with m.Switch(self.sel_in):
 183             with m.Case(In3Sel.RB):
 184                 comb += self.reg_out.data.eq(self.dec.RB) # for M-Form shiftrot
 185                 comb += self.reg_out.ok.eq(1)
 186             with m.Case(In3Sel.RS):
 187                 comb += self.reg_out.data.eq(self.dec.RS)
 188                 comb += self.reg_out.ok.eq(1)
 189
 190         return m
 191
 192
 193 class DecodeOut(Elaboratable):
 194     """DecodeOut from instruction
 195
 196     decodes output register RA, RT or SPR
 197     """
 198
 199     def __init__(self, dec):
 200         self.dec = dec
 201         self.sel_in = Signal(OutSel, reset_less=True)
 202         self.insn_in = Signal(32, reset_less=True)
 203         self.reg_out = Data(5, "reg_o")
 204         self.spr_out = Data(10, "spr_o")
 205
 206     def elaborate(self, platform):
 207         m = Module()
 208         comb = m.d.comb
 209
 210         # select Register out field
 211         with m.Switch(self.sel_in):
 212             with m.Case(OutSel.RT):
 213                 comb += self.reg_out.data.eq(self.dec.RT)
 214                 comb += self.reg_out.ok.eq(1)
 215             with m.Case(OutSel.RA):
 216                 comb += self.reg_out.data.eq(self.dec.RA)
 217                 comb += self.reg_out.ok.eq(1)
 218             with m.Case(OutSel.SPR):
 219                 comb += self.spr_out.data.eq(self.dec.SPR) # from XFX
 220                 comb += self.spr_out.ok.eq(1)
 221
 222         return m
 223
 224
 225 class DecodeRC(Elaboratable):
 226     """DecodeRc from instruction
 227
 228     decodes Record bit Rc
 229     """
 230     def __init__(self, dec):
 231         self.dec = dec
 232         self.sel_in = Signal(RC, reset_less=True)
 233         self.insn_in = Signal(32, reset_less=True)
 234         self.rc_out = Data(1, "rc")
 235
 236     def elaborate(self, platform):
 237         m = Module()
 238         comb = m.d.comb
 239
 240         # select Record bit out field
 241         with m.Switch(self.sel_in):
 242             with m.Case(RC.RC):
 243                 comb += self.rc_out.data.eq(self.dec.Rc)
 244                 comb += self.rc_out.ok.eq(1)
 245             with m.Case(RC.ONE):
 246                 comb += self.rc_out.data.eq(1)
 247                 comb += self.rc_out.ok.eq(1)
 248             with m.Case(RC.NONE):
 249                 comb += self.rc_out.data.eq(0)
 250                 comb += self.rc_out.ok.eq(1)
 251
 252         return m
 253
 254
 255 class DecodeOE(Elaboratable):
 256     """DecodeOE from instruction
 257
 258     decodes OE field: uses RC decode detection which might not be good
 259
 260     -- For now, use "rc" in the decode table to decide whether oe exists.
 261     -- This is not entirely correct architecturally: For mulhd and
 262     -- mulhdu, the OE field is reserved. It remains to be seen what an
 263     -- actual POWER9 does if we set it on those instructions, for now we
 264     -- test that further down when assigning to the multiplier oe input.
 265     """
 266     def __init__(self, dec):
 267         self.dec = dec
 268         self.sel_in = Signal(RC, reset_less=True)
 269         self.insn_in = Signal(32, reset_less=True)
 270         self.oe_out = Data(1, "oe")
 271
 272     def elaborate(self, platform):
 273         m = Module()
 274         comb = m.d.comb
 275
 276         # select OE bit out field
 277         with m.Switch(self.sel_in):
 278             with m.Case(RC.RC):
 279                 comb += self.oe_out.data.eq(self.dec.OE)
 280                 comb += self.oe_out.ok.eq(1)
 281
 282         return m
 283
 284 class DecodeCRIn(Elaboratable):
 285     """Decodes input CR from instruction
 286
 287     CR indices - insn fields - (not the data *in* the CR) require only 3
 288     bits because they refer to CR0-CR7
 289     """
 290
 291     def __init__(self, dec):
 292         self.dec = dec
 293         self.sel_in = Signal(CRInSel, reset_less=True)
 294         self.insn_in = Signal(32, reset_less=True)
 295         self.cr_bitfield = Data(3, "cr_bitfield")
 296         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 297         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 298         self.whole_reg = Signal(reset_less=True)
 299
 300     def elaborate(self, platform):
 301         m = Module()
 302         comb = m.d.comb
 303
 304         comb += self.cr_bitfield.ok.eq(0)
 305         comb += self.cr_bitfield_b.ok.eq(0)
 306         comb += self.whole_reg.eq(0)
 307         with m.Switch(self.sel_in):
 308             with m.Case(CRInSel.NONE):
 309                 pass # No bitfield activated
 310             with m.Case(CRInSel.CR0):
 311                 comb += self.cr_bitfield.data.eq(0)
 312                 comb += self.cr_bitfield.ok.eq(1)
 313             with m.Case(CRInSel.BI):
 314                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 315                 comb += self.cr_bitfield.ok.eq(1)
 316             with m.Case(CRInSel.BFA):
 317                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 318                 comb += self.cr_bitfield.ok.eq(1)
 319             with m.Case(CRInSel.BA_BB):
 320                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 321                 comb += self.cr_bitfield.ok.eq(1)
 322                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 323                 comb += self.cr_bitfield_b.ok.eq(1)
 324                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 325                 comb += self.cr_bitfield_o.ok.eq(1)
 326             with m.Case(CRInSel.BC):
 327                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 328                 comb += self.cr_bitfield.ok.eq(1)
 329             with m.Case(CRInSel.WHOLE_REG):
 330                 comb += self.whole_reg.eq(1)
 331
 332         return m
 333
 334
 335 class DecodeCROut(Elaboratable):
 336     """Decodes input CR from instruction
 337
 338     CR indices - insn fields - (not the data *in* the CR) require only 3
 339     bits because they refer to CR0-CR7
 340     """
 341
 342     def __init__(self, dec):
 343         self.dec = dec
 344         self.rc_in = Signal(reset_less=True)
 345         self.sel_in = Signal(CROutSel, reset_less=True)
 346         self.insn_in = Signal(32, reset_less=True)
 347         self.cr_bitfield = Data(3, "cr_bitfield")
 348         self.whole_reg = Signal(reset_less=True)
 349
 350     def elaborate(self, platform):
 351         m = Module()
 352         comb = m.d.comb
 353
 354         comb += self.cr_bitfield.ok.eq(0)
 355         comb += self.whole_reg.eq(0)
 356         with m.Switch(self.sel_in):
 357             with m.Case(CROutSel.NONE):
 358                 pass # No bitfield activated
 359             with m.Case(CROutSel.CR0):
 360                 comb += self.cr_bitfield.data.eq(0)
 361                 comb += self.cr_bitfield.ok.eq(self.rc_in) # only when RC=1
 362             with m.Case(CROutSel.BF):
 363                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF[0:-1])
 364                 comb += self.cr_bitfield.ok.eq(1)
 365             with m.Case(CROutSel.BT):
 366                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 367                 comb += self.cr_bitfield.ok.eq(1)
 368             with m.Case(CROutSel.WHOLE_REG):
 369                 comb += self.whole_reg.eq(1)
 370
 371         return m
 372
 373
 374 class XerBits:
 375     def __init__(self):
 376         self.ca = Signal(2, reset_less=True)
 377         self.ov = Signal(2, reset_less=True)
 378         self.so = Signal(reset_less=True)
 379
 380     def ports(self):
 381         return [self.ca, self.ov, self.so]
 382
 383
 384 class Decode2ToExecute1Type(RecordObject):
 385
 386     def __init__(self, name=None):
 387
 388         RecordObject.__init__(self, name=name)
 389
 390         self.valid = Signal(reset_less=True)
 391         self.insn_type = Signal(InternalOp, reset_less=True)
 392         self.fn_unit = Signal(Function, reset_less=True)
 393         self.nia = Signal(64, reset_less=True)
 394         self.write_reg = Data(5, name="rego")
 395         self.read_reg1 = Data(5, name="reg1")
 396         self.read_reg2 = Data(5, name="reg2")
 397         self.read_reg3 = Data(5, name="reg3")
 398         self.imm_data = Data(64, name="imm")
 399         self.write_spr = Data(10, name="spro")
 400         self.read_spr1 = Data(10, name="spr1")
 401         self.read_spr2 = Data(10, name="spr2")
 402
 403         self.read_cr1 = Data(3, name="cr_in1")
 404         self.read_cr2 = Data(3, name="cr_in2")
 405         self.read_cr3 = Data(3, name="cr_in2")
 406         self.read_cr_whole = Signal(reset_less=True)
 407         self.write_cr = Data(3, name="cr_out")
 408         self.write_cr_whole = Signal(reset_less=True)
 409         self.lk = Signal(reset_less=True)
 410         self.rc = Data(1, "rc")
 411         self.oe = Data(1, "oe")
 412         self.invert_a = Signal(reset_less=True)
 413         self.zero_a = Signal(reset_less=True)
 414         self.invert_out = Signal(reset_less=True)
 415         self.input_carry = Signal(CryIn, reset_less=True)
 416         self.output_carry = Signal(reset_less=True)
 417         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
 418         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
 419         self.is_32bit = Signal(reset_less=True)
 420         self.is_signed = Signal(reset_less=True)
 421         self.insn = Signal(32, reset_less=True)
 422         self.data_len = Signal(4, reset_less=True) # bytes
 423         self.byte_reverse  = Signal(reset_less=True)
 424         self.sign_extend  = Signal(reset_less=True)# do we need this?
 425         self.update  = Signal(reset_less=True) # LD/ST is "update" variant
 426
 427
 428 class PowerDecode2(Elaboratable):
 429
 430     def __init__(self, dec):
 431
 432         self.dec = dec
 433         self.e = Decode2ToExecute1Type()
 434
 435     def ports(self):
 436         return self.dec.ports() + self.e.ports()
 437
 438     def elaborate(self, platform):
 439         m = Module()
 440         comb = m.d.comb
 441
 442         # set up submodule decoders
 443         m.submodules.dec = self.dec
 444         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 445         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 446         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 447         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 448         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 449         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 450         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 451         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 452
 453         # copy instruction through...
 454         for i in [self.e.insn, dec_a.insn_in, dec_b.insn_in,
 455                   dec_c.insn_in, dec_o.insn_in, dec_rc.insn_in,
 456                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 457             comb += i.eq(self.dec.opcode_in)
 458
 459         # ...and subdecoders' input fields
 460         comb += dec_a.sel_in.eq(self.dec.op.in1_sel)
 461         comb += dec_b.sel_in.eq(self.dec.op.in2_sel)
 462         comb += dec_c.sel_in.eq(self.dec.op.in3_sel)
 463         comb += dec_o.sel_in.eq(self.dec.op.out_sel)
 464         comb += dec_rc.sel_in.eq(self.dec.op.rc_sel)
 465         comb += dec_oe.sel_in.eq(self.dec.op.rc_sel) # XXX should be OE sel
 466         comb += dec_cr_in.sel_in.eq(self.dec.op.cr_in)
 467         comb += dec_cr_out.sel_in.eq(self.dec.op.cr_out)
 468         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 469
 470         # decode LD/ST length
 471         with m.Switch(self.dec.op.ldst_len):
 472             with m.Case(LdstLen.is1B):
 473                 comb += self.e.data_len.eq(1)
 474             with m.Case(LdstLen.is2B):
 475                 comb += self.e.data_len.eq(2)
 476             with m.Case(LdstLen.is4B):
 477                 comb += self.e.data_len.eq(4)
 478             with m.Case(LdstLen.is8B):
 479                 comb += self.e.data_len.eq(8)
 480
 481         comb += self.e.nia.eq(0)    # XXX TODO
 482         comb += self.e.valid.eq(0)  # XXX TODO
 483         fu = self.dec.op.function_unit
 484         itype = Mux(fu == Function.NONE,
 485                     InternalOp.OP_ILLEGAL,
 486                     self.dec.op.internal_op)
 487         comb += self.e.insn_type.eq(itype)
 488         comb += self.e.fn_unit.eq(fu)
 489
 490         # registers a, b, c and out
 491         comb += self.e.read_reg1.eq(dec_a.reg_out)
 492         comb += self.e.read_reg2.eq(dec_b.reg_out)
 493         comb += self.e.read_reg3.eq(dec_c.reg_out)
 494         comb += self.e.write_reg.eq(dec_o.reg_out)
 495         comb += self.e.imm_data.eq(dec_b.imm_out) # immediate in RB (usually)
 496         comb += self.e.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 497
 498         # rc and oe out
 499         comb += self.e.rc.eq(dec_rc.rc_out)
 500         comb += self.e.oe.eq(dec_oe.oe_out)
 501
 502         # SPRs out
 503         comb += self.e.read_spr1.eq(dec_a.spr_out)
 504         comb += self.e.read_spr2.eq(dec_b.spr_out)
 505         comb += self.e.write_spr.eq(dec_o.spr_out)
 506
 507         comb += self.e.read_cr1.eq(dec_cr_in.cr_bitfield)
 508         comb += self.e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 509         comb += self.e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 510         comb += self.e.read_cr_whole.eq(dec_cr_in.whole_reg)
 511
 512         comb += self.e.write_cr.eq(dec_cr_out.cr_bitfield)
 513         comb += self.e.write_cr_whole.eq(dec_cr_out.whole_reg)
 514
 515         # decoded/selected instruction flags
 516         comb += self.e.invert_a.eq(self.dec.op.inv_a)
 517         comb += self.e.invert_out.eq(self.dec.op.inv_out)
 518         comb += self.e.input_carry.eq(self.dec.op.cry_in)   # carry comes in
 519         comb += self.e.output_carry.eq(self.dec.op.cry_out) # carry goes out
 520         comb += self.e.is_32bit.eq(self.dec.op.is_32b)
 521         comb += self.e.is_signed.eq(self.dec.op.sgn)
 522         with m.If(self.dec.op.lk):
 523             comb += self.e.lk.eq(self.dec.LK) # XXX TODO: accessor
 524
 525         comb += self.e.byte_reverse.eq(self.dec.op.br)
 526         comb += self.e.sign_extend.eq(self.dec.op.sgn_ext)
 527         comb += self.e.update.eq(self.dec.op.upd) # LD/ST "update" mode
 528
 529
 530
 531         # These should be removed eventually
 532         comb += self.e.input_cr.eq(self.dec.op.cr_in)   # condition reg comes in
 533         comb += self.e.output_cr.eq(self.dec.op.cr_out) # condition reg goes in
 534
 535
 536         return m
 537
 538
 539 if __name__ == '__main__':
 540     pdecode = create_pdecode()
 541     dec2 = PowerDecode2(pdecode)
 542     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 543     with open("dec2.il", "w") as f:
 544         f.write(vl)
 545