src/soc/litex/florent/versa_ecp5.py

   1 #!/usr/bin/env python3
   2
   3 import os
   4 import argparse
   5
   6 import litex_boards.targets.versa_ecp5 as versa_ecp5
   7 import litex_boards.targets.ulx3s as ulx3s
   8
   9 from litex.soc.integration.soc_sdram import (soc_sdram_args,
  10                                              soc_sdram_argdict)
  11 from litex.soc.integration.builder import (Builder, builder_args,
  12                                            builder_argdict)
  13
  14 from libresoc import LibreSoC
  15 #from microwatt import Microwatt
  16
  17 # TestSoC
  18 # ----------------------------------------------------------------------------
  19
  20 class VersaECP5TestSoC(versa_ecp5.BaseSoC):
  21     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  22         kwargs["integrated_rom_size"] = 0x10000
  23         #kwargs["integrated_main_ram_size"] = 0x1000
  24         kwargs["csr_data_width"] = 32
  25         kwargs["l2_size"] = 0
  26         #bus_data_width = 16,
  27
  28         versa_ecp5.BaseSoC.__init__(self,
  29             sys_clk_freq = sys_clk_freq,
  30             cpu_type     = "external",
  31             cpu_cls      = LibreSoC,
  32             cpu_variant = "standardjtagnoirq",
  33             #cpu_cls      = Microwatt,
  34             device       = "LFE5UM",
  35             **kwargs)
  36
  37         if False: # well that didn't work.  connectors are different
  38                   # from platform IO.
  39             # get 4 arbitrarily-selected pins from the X3 connector
  40             jtag_tck = self.platform.request("X3", "B19")
  41             jtag_tms = self.platform.request("X3", "B12")
  42             jtag_tdi = self.platform.request("X3", "B9")
  43             jtag_tdo = self.platform.request("X3", "E6")
  44
  45             # wire the pins up to CPU JTAG
  46             self.comb += self.cpu.jtag_tck.eq(jtag_tck)
  47             self.comb += self.cpu.jtag_tms.eq(jtag_tms)
  48             self.comb += self.cpu.jtag_tdi.eq(jtag_tdi)
  49             self.comb += jtag_tdo.eq(self.cpu.jtag_tdo)
  50
  51
  52         #self.add_constant("MEMTEST_BUS_SIZE",  256//16)
  53         #self.add_constant("MEMTEST_DATA_SIZE", 256//16)
  54         #self.add_constant("MEMTEST_ADDR_SIZE", 256//16)
  55
  56         #self.add_constant("MEMTEST_BUS_DEBUG", 1)
  57         #self.add_constant("MEMTEST_ADDR_DEBUG", 1)
  58         #self.add_constant("MEMTEST_DATA_DEBUG", 1)
  59
  60 class ULX3S85FTestSoC(ulx3s.BaseSoC):
  61     def __init__(self, sys_clk_freq=int(16e6), **kwargs):
  62         kwargs["integrated_rom_size"] = 0x10000
  63         #kwargs["integrated_main_ram_size"] = 0x1000
  64         kwargs["csr_data_width"] = 32
  65         kwargs["l2_size"] = 0
  66         #bus_data_width = 16,
  67
  68         ulx3s.BaseSoC.__init__(self,
  69             sys_clk_freq = sys_clk_freq,
  70             cpu_type     = "external",
  71             cpu_cls      = LibreSoC,
  72             cpu_variant  = "standardjtag",
  73             #cpu_cls      = Microwatt,
  74             device       = "LFE5U-85F",
  75             **kwargs)
  76
  77 # Build
  78 # ----------------------------------------------------------------------------
  79
  80 def main():
  81     parser = argparse.ArgumentParser(description="LiteX SoC with LibreSoC " \
  82                                      "CPU on Versa ECP5 or ULX3S LFE5U85F")
  83     parser.add_argument("--build", action="store_true", help="Build bitstream")
  84     parser.add_argument("--load", action="store_true", help="Load bitstream")
  85     parser.add_argument("--sys-clk-freq",  default=int(16e6),
  86                         help="System clock frequency (default=16MHz)")
  87     parser.add_argument("--fpga", default="versa_ecp5", help="FPGA target " \
  88                         "to build for/load to")
  89
  90     builder_args(parser)
  91     soc_sdram_args(parser)
  92     args = parser.parse_args()
  93
  94     if args.fpga == "versa_ecp5":
  95         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
  96                                **soc_sdram_argdict(args))
  97
  98     elif args.fpga == "ulx3s85f":
  99         soc = ULX3S85FTestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 100                               **soc_sdram_argdict(args))
 101
 102     else:
 103         soc = VersaECP5TestSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
 104                                **soc_sdram_argdict(args))
 105
 106     builder = Builder(soc, **builder_argdict(args))
 107     builder.build(run=args.build)
 108
 109     if args.load:
 110         prog = soc.platform.create_programmer()
 111         prog.load_bitstream(os.path.join(builder.gateware_dir,
 112                                          soc.build_name + ".svf"))
 113
 114 if __name__ == "__main__":
 115     main()