021e4fa3bc2483b98c44e518d60616b90af1c81f
3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
22 from nmigen
import Elaboratable
, Module
, Signal
, ResetSignal
, Cat
, Mux
23 from nmigen
.cli
import rtlil
25 from openpower
.decoder
.power_decoder2
import PowerDecodeSubset
26 from openpower
.decoder
.power_regspec_map
import regspec_decode_read
27 from openpower
.decoder
.power_regspec_map
import regspec_decode_write
28 from openpower
.sv
.svp64
import SVP64Rec
30 from nmutil
.picker
import PriorityPicker
31 from nmutil
.util
import treereduce
32 from nmutil
.singlepipe
import ControlBase
34 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
, LDSTFunctionUnit
35 from soc
.regfile
.regfiles
import RegFiles
36 from openpower
.decoder
.power_decoder2
import get_rdflags
37 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
38 from soc
.config
.test
.test_loadstore
import TestMemPspec
39 from openpower
.decoder
.power_enums
import MicrOp
, Function
40 from soc
.simple
.core_data
import CoreInput
, CoreOutput
42 from collections
import defaultdict
45 from nmutil
.util
import rising_edge
48 # helper function for reducing a list of signals down to a parallel
50 def ortreereduce(tree
, attr
="o_data"):
51 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
54 def ortreereduce_sig(tree
):
55 return treereduce(tree
, operator
.or_
, lambda x
: x
)
58 # helper function to place full regs declarations first
59 def sort_fuspecs(fuspecs
):
61 for (regname
, fspec
) in fuspecs
.items():
62 if regname
.startswith("full"):
63 res
.append((regname
, fspec
))
64 for (regname
, fspec
) in fuspecs
.items():
65 if not regname
.startswith("full"):
66 res
.append((regname
, fspec
))
67 return res
# enumerate(res)
70 # derive from ControlBase rather than have a separate Stage instance,
71 # this is simpler to do
72 class NonProductionCore(ControlBase
):
73 def __init__(self
, pspec
):
76 # test is SVP64 is to be enabled
77 self
.svp64_en
= hasattr(pspec
, "svp64") and (pspec
.svp64
== True)
79 # test to see if regfile ports should be reduced
80 self
.regreduce_en
= (hasattr(pspec
, "regreduce") and
81 (pspec
.regreduce
== True))
83 # test to see if overlapping of instructions is allowed
84 # (not normally enabled for TestIssuer FSM but useful for checking
85 # the bitvector hazard detection, before doing In-Order)
86 self
.allow_overlap
= (hasattr(pspec
, "allow_overlap") and
87 (pspec
.allow_overlap
== True))
90 self
.make_hazard_vecs
= True
91 self
.core_type
= "fsm"
92 if hasattr(pspec
, "core_type"):
93 self
.core_type
= pspec
.core_type
95 super().__init
__(stage
=self
)
97 # single LD/ST funnel for memory access
98 self
.l0
= l0
= TstL0CacheBuffer(pspec
, n_units
=1)
101 # function units (only one each)
102 # only include mmu if enabled in pspec
103 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
105 # link LoadStore1 into MMU
106 mmu
= self
.fus
.get_fu('mmu0')
107 print ("core pspec", pspec
.ldst_ifacetype
)
108 print ("core mmu", mmu
)
110 print ("core lsmem.lsi", l0
.cmpi
.lsmem
.lsi
)
111 mmu
.alu
.set_ldst_interface(l0
.cmpi
.lsmem
.lsi
)
113 # register files (yes plural)
114 self
.regs
= RegFiles(pspec
, make_hazard_vecs
=self
.make_hazard_vecs
)
116 # set up input and output: unusual requirement to set data directly
117 # (due to the way that the core is set up in a different domain,
118 # see TestIssuer.setup_peripherals
119 self
.p
.i_data
, self
.n
.o_data
= self
.new_specs(None)
120 self
.i
, self
.o
= self
.p
.i_data
, self
.n
.o_data
122 # actual internal input data used (captured)
123 self
.ireg
= self
.ispec()
125 # create per-FU instruction decoders (subsetted). these "satellite"
126 # decoders reduce wire fan-out from the one (main) PowerDecoder2
127 # (used directly by the trap unit) to the *twelve* (or more)
128 # Function Units. we can either have 32 wires (the instruction)
129 # to each, or we can have well over a 200 wire fan-out (to 12
130 # ALUs). it's an easy choice to make.
134 for funame
, fu
in self
.fus
.fus
.items():
135 f_name
= fu
.fnunit
.name
136 fnunit
= fu
.fnunit
.value
137 opkls
= fu
.opsubsetkls
139 # TRAP decoder is the *main* decoder
140 self
.trapunit
= funame
142 self
.decoders
[funame
] = PowerDecodeSubset(None, opkls
, f_name
,
144 state
=self
.ireg
.state
,
145 svp64_en
=self
.svp64_en
,
146 regreduce_en
=self
.regreduce_en
)
147 self
.des
[funame
] = self
.decoders
[funame
].do
149 # share the SPR decoder with the MMU if it exists
150 if "mmu0" in self
.decoders
:
151 self
.decoders
["mmu0"].mmu0_spr_dec
= self
.decoders
["spr0"]
153 # next 3 functions are Stage API Compliance
154 def setup(self
, m
, i
):
158 return CoreInput(self
.pspec
, self
.svp64_en
, self
.regreduce_en
)
163 # elaborate function to create HDL
164 def elaborate(self
, platform
):
165 m
= super().elaborate(platform
)
167 # for testing purposes, to cut down on build time in coriolis2
168 if hasattr(self
.pspec
, "nocore") and self
.pspec
.nocore
== True:
169 x
= Signal() # dummy signal
174 m
.submodules
.fus
= self
.fus
175 m
.submodules
.l0
= l0
= self
.l0
176 self
.regs
.elaborate_into(m
, platform
)
181 self
.connect_satellite_decoders(m
)
183 # ssh, cheat: trap uses the main decoder because of the rewriting
184 self
.des
[self
.trapunit
] = self
.ireg
.e
.do
186 # connect up Function Units, then read/write ports, and hazard conflict
187 issue_conflict
= Signal()
188 fu_bitdict
, fu_selected
= self
.connect_instruction(m
, issue_conflict
)
189 raw_hazard
= self
.connect_rdports(m
, fu_selected
)
190 self
.connect_wrports(m
, fu_selected
)
191 if self
.allow_overlap
:
192 comb
+= issue_conflict
.eq(raw_hazard
)
194 # note if an exception happened. in a pipelined or OoO design
195 # this needs to be accompanied by "shadowing" (or stalling)
197 for exc
in self
.fus
.excs
.values():
198 el
.append(exc
.happened
)
199 if len(el
) > 0: # at least one exception
200 comb
+= self
.o
.exc_happened
.eq(Cat(*el
).bool())
204 def connect_satellite_decoders(self
, m
):
206 for k
, v
in self
.decoders
.items():
207 # connect each satellite decoder and give it the instruction.
208 # as subset decoders this massively reduces wire fanout given
209 # the large number of ALUs
210 setattr(m
.submodules
, "dec_%s" % v
.fn_name
, v
)
211 comb
+= v
.dec
.raw_opcode_in
.eq(self
.ireg
.raw_insn_i
)
212 comb
+= v
.dec
.bigendian
.eq(self
.ireg
.bigendian_i
)
213 # sigh due to SVP64 RA_OR_ZERO detection connect these too
214 comb
+= v
.sv_a_nz
.eq(self
.ireg
.sv_a_nz
)
216 comb
+= v
.pred_sm
.eq(self
.ireg
.sv_pred_sm
)
217 comb
+= v
.pred_dm
.eq(self
.ireg
.sv_pred_dm
)
218 if k
!= self
.trapunit
:
219 comb
+= v
.sv_rm
.eq(self
.ireg
.sv_rm
) # pass through SVP64 RM
220 comb
+= v
.is_svp64_mode
.eq(self
.ireg
.is_svp64_mode
)
221 # only the LDST PowerDecodeSubset *actually* needs to
222 # know to use the alternative decoder. this is all
224 if k
.lower().startswith("ldst"):
225 comb
+= v
.use_svp64_ldst_dec
.eq(
226 self
.ireg
.use_svp64_ldst_dec
)
228 def connect_instruction(self
, m
, issue_conflict
):
229 """connect_instruction
231 uses decoded (from PowerOp) function unit information from CSV files
232 to ascertain which Function Unit should deal with the current
235 some (such as OP_ATTN, OP_NOP) are dealt with here, including
236 ignoring it and halting the processor. OP_NOP is a bit annoying
237 because the issuer expects busy flag still to be raised then lowered.
238 (this requires a fake counter to be set).
240 comb
, sync
= m
.d
.comb
, m
.d
.sync
243 # indicate if core is busy
244 busy_o
= self
.o
.busy_o
246 # connect up temporary copy of incoming instruction. the FSM will
247 # either blat the incoming instruction (if valid) into self.ireg
248 # or if the instruction could not be delivered, keep dropping the
249 # latched copy into ireg
250 ilatch
= self
.ispec()
251 self
.instr_active
= Signal()
253 # enable/busy-signals for each FU, get one bit for each FU (by name)
254 fu_enable
= Signal(len(fus
), reset_less
=True)
255 fu_busy
= Signal(len(fus
), reset_less
=True)
258 for i
, funame
in enumerate(fus
.keys()):
259 fu_bitdict
[funame
] = fu_enable
[i
]
260 fu_selected
[funame
] = fu_busy
[i
]
262 # identify function units and create a list by fnunit so that
263 # PriorityPickers can be created for selecting one of them that
264 # isn't busy at the time the incoming instruction needs passing on
265 by_fnunit
= defaultdict(list)
266 for fname
, member
in Function
.__members
__.items():
267 for funame
, fu
in fus
.items():
268 fnunit
= fu
.fnunit
.value
269 if member
.value
& fnunit
: # this FU handles this type of op
270 by_fnunit
[fname
].append((funame
, fu
)) # add by Function
272 # ok now just print out the list of FUs by Function, because we can
273 for fname
, fu_list
in by_fnunit
.items():
274 print ("FUs by type", fname
, fu_list
)
276 # now create a PriorityPicker per FU-type such that only one
277 # non-busy FU will be picked
279 fu_found
= Signal() # take a note if no Function Unit was available
280 for fname
, fu_list
in by_fnunit
.items():
281 i_pp
= PriorityPicker(len(fu_list
))
282 m
.submodules
['i_pp_%s' % fname
] = i_pp
284 for i
, (funame
, fu
) in enumerate(fu_list
):
285 # match the decoded instruction (e.do.fn_unit) against the
286 # "capability" of this FU, gate that by whether that FU is
287 # busy, and drop that into the PriorityPicker.
288 # this will give us an output of the first available *non-busy*
289 # Function Unit (Reservation Statio) capable of handling this
291 fnunit
= fu
.fnunit
.value
292 en_req
= Signal(name
="issue_en_%s" % funame
, reset_less
=True)
293 fnmatch
= (self
.ireg
.e
.do
.fn_unit
& fnunit
).bool()
294 comb
+= en_req
.eq(fnmatch
& ~fu
.busy_o
& self
.instr_active
)
295 i_l
.append(en_req
) # store in list for doing the Cat-trick
296 # picker output, gated by enable: store in fu_bitdict
297 po
= Signal(name
="o_issue_pick_"+funame
) # picker output
298 comb
+= po
.eq(i_pp
.o
[i
] & i_pp
.en_o
)
299 comb
+= fu_bitdict
[funame
].eq(po
)
300 comb
+= fu_selected
[funame
].eq(fu
.busy_o | po
)
301 # if we don't do this, then when there are no FUs available,
302 # the "p.o_ready" signal will go back "ok we accepted this
303 # instruction" which of course isn't true.
304 with m
.If(~issue_conflict
& i_pp
.en_o
):
305 comb
+= fu_found
.eq(1)
306 # for each input, Cat them together and drop them into the picker
307 comb
+= i_pp
.i
.eq(Cat(*i_l
))
309 # rdmask, which is for registers needs to come from the *main* decoder
310 for funame
, fu
in fus
.items():
311 rdmask
= get_rdflags(self
.ireg
.e
, fu
)
312 comb
+= fu
.rdmaskn
.eq(~rdmask
)
314 # sigh - need a NOP counter
316 with m
.If(counter
!= 0):
317 sync
+= counter
.eq(counter
- 1)
320 # default to reading from incoming instruction: may be overridden
321 # by copy from latch when "waiting"
322 comb
+= self
.ireg
.eq(self
.i
)
323 # always say "ready" except if overridden
324 comb
+= self
.p
.o_ready
.eq(1)
326 l_issue_conflict
= Signal()
329 with m
.State("READY"):
330 with m
.If(self
.p
.i_valid
): # run only when valid
331 with m
.Switch(self
.ireg
.e
.do
.insn_type
):
332 # check for ATTN: halt if true
333 with m
.Case(MicrOp
.OP_ATTN
):
334 m
.d
.sync
+= self
.o
.core_terminate_o
.eq(1)
336 # fake NOP - this isn't really used (Issuer detects NOP)
337 with m
.Case(MicrOp
.OP_NOP
):
338 sync
+= counter
.eq(2)
342 comb
+= self
.instr_active
.eq(1)
343 comb
+= self
.p
.o_ready
.eq(0)
344 # connect instructions. only one enabled at a time
345 for funame
, fu
in fus
.items():
346 do
= self
.des
[funame
]
347 enable
= fu_bitdict
[funame
]
349 # run this FunctionUnit if enabled route op,
350 # issue, busy, read flags and mask to FU
351 with m
.If(enable
& ~issue_conflict
):
352 # operand comes from the *local* decoder
353 comb
+= fu
.oper_i
.eq_from(do
)
354 comb
+= fu
.issue_i
.eq(1) # issue when valid
355 # instruction ok, indicate ready
356 comb
+= self
.p
.o_ready
.eq(1)
358 if self
.allow_overlap
:
359 with m
.If(~fu_found
):
360 # latch copy of instruction
361 sync
+= ilatch
.eq(self
.i
)
362 sync
+= l_issue_conflict
.eq(issue_conflict
)
363 comb
+= self
.p
.o_ready
.eq(1) # accept
367 with m
.State("WAITING"):
368 comb
+= self
.instr_active
.eq(1)
370 sync
+= l_issue_conflict
.eq(0)
371 comb
+= self
.p
.o_ready
.eq(0)
373 # using copy of instruction, keep waiting until an FU is free
374 comb
+= self
.ireg
.eq(ilatch
)
375 with m
.If(~l_issue_conflict
): # wait for conflict to clear
376 # connect instructions. only one enabled at a time
377 for funame
, fu
in fus
.items():
378 do
= self
.des
[funame
]
379 enable
= fu_bitdict
[funame
]
381 # run this FunctionUnit if enabled route op,
382 # issue, busy, read flags and mask to FU
384 # operand comes from the *local* decoder
385 comb
+= fu
.oper_i
.eq_from(do
)
386 comb
+= fu
.issue_i
.eq(1) # issue when valid
387 comb
+= self
.p
.o_ready
.eq(1)
391 print ("core: overlap allowed", self
.allow_overlap
)
392 if not self
.allow_overlap
:
393 # for simple non-overlap, if any instruction is busy, set
394 # busy output for core.
395 busys
= map(lambda fu
: fu
.busy_o
, fus
.values())
396 comb
+= busy_o
.eq(Cat(*busys
).bool())
398 # return both the function unit "enable" dict as well as the "busy".
399 # the "busy-or-issued" can be passed in to the Read/Write port
400 # connecters to give them permission to request access to regfiles
401 return fu_bitdict
, fu_selected
403 def connect_rdport(self
, m
, fu_bitdict
, rdpickers
, regfile
, regname
, fspec
):
404 comb
, sync
= m
.d
.comb
, m
.d
.sync
410 # select the required read port. these are pre-defined sizes
411 rfile
= regs
.rf
[regfile
.lower()]
412 rport
= rfile
.r_ports
[rpidx
]
413 print("read regfile", rpidx
, regfile
, regs
.rf
.keys(),
416 # for checking if the read port has an outstanding write
417 if self
.make_hazard_vecs
:
418 wv
= regs
.wv
[regfile
.lower()]
419 wvchk
= wv
.r_ports
["issue"] # write-vec bit-level hazard check
422 if not isinstance(fspecs
, list):
428 for i
, fspec
in enumerate(fspecs
):
429 # get the regfile specs for this regfile port
430 (rf
, wf
, read
, write
, wid
, fuspec
) = fspec
431 print ("fpsec", i
, fspec
, len(fuspec
))
432 ppoffs
.append(pplen
) # record offset for picker
434 name
= "rdflag_%s_%s_%d" % (regfile
, regname
, i
)
435 rdflag
= Signal(name
=name
, reset_less
=True)
436 comb
+= rdflag
.eq(rf
)
437 rdflags
.append(rdflag
)
439 print ("pplen", pplen
)
441 # create a priority picker to manage this port
442 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(pplen
)
443 setattr(m
.submodules
, "rdpick_%s_%s" % (regfile
, rpidx
), rdpick
)
449 for i
, fspec
in enumerate(fspecs
):
450 (rf
, wf
, _read
, _write
, wid
, fuspec
) = fspec
451 # connect up the FU req/go signals, and the reg-read to the FU
452 # and create a Read Broadcast Bus
453 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
455 name
= "%s_%s_%s_%i" % (regfile
, rpidx
, funame
, pi
)
456 fu_active
= fu_bitdict
[funame
]
458 # get (or set up) a latched copy of read register number
459 rname
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, pi
)
460 read
= Signal
.like(_read
, name
="read_"+name
)
461 if rname
not in fu
.rd_latches
:
462 rdl
= Signal
.like(_read
, name
="rdlatch_"+rname
)
463 fu
.rd_latches
[rname
] = rdl
464 with m
.If(fu
.issue_i
):
465 sync
+= rdl
.eq(_read
)
467 rdl
= fu
.rd_latches
[rname
]
468 # latch to make the read immediately available on issue cycle
469 # after the read cycle, use the latched copy
470 with m
.If(fu
.issue_i
):
471 comb
+= read
.eq(_read
)
475 # connect request-read to picker input, and output to go-rd
476 addr_en
= Signal
.like(read
, name
="addr_en_"+name
)
477 pick
= Signal(name
="pick_"+name
) # picker input
478 rp
= Signal(name
="rp_"+name
) # picker output
479 delay_pick
= Signal(name
="dp_"+name
) # read-enable "underway"
481 # exclude any currently-enabled read-request (mask out active)
482 comb
+= pick
.eq(fu
.rd_rel_o
[idx
] & fu_active
& rdflags
[i
] &
484 comb
+= rdpick
.i
[pi
].eq(pick
)
485 comb
+= fu
.go_rd_i
[idx
].eq(delay_pick
) # pass in *delayed* pick
487 # if picked, select read-port "reg select" number to port
488 comb
+= rp
.eq(rdpick
.o
[pi
] & rdpick
.en_o
)
489 sync
+= delay_pick
.eq(rp
) # delayed "pick"
490 comb
+= addr_en
.eq(Mux(rp
, read
, 0))
492 # the read-enable happens combinatorially (see mux-bus below)
493 # but it results in the data coming out on a one-cycle delay.
497 addrs
.append(addr_en
)
500 # use the *delayed* pick signal to put requested data onto bus
501 with m
.If(delay_pick
):
502 # connect regfile port to input, creating fan-out Bus
504 print("reg connect widths",
505 regfile
, regname
, pi
, funame
,
506 src
.shape(), rport
.o_data
.shape())
507 # all FUs connect to same port
508 comb
+= src
.eq(rport
.o_data
)
510 if not self
.make_hazard_vecs
:
513 # read the write-hazard bitvector (wv) for any bit that is
514 wvchk_en
= Signal(len(wvchk
.ren
), name
="wv_chk_addr_en_"+name
)
515 issue_active
= Signal(name
="rd_iactive_"+name
)
516 # XXX combinatorial loop here
517 comb
+= issue_active
.eq(self
.instr_active
& rf
)
518 with m
.If(issue_active
):
520 comb
+= wvchk_en
.eq(read
)
522 comb
+= wvchk_en
.eq(1<<read
)
523 wvens
.append(wvchk_en
)
525 # or-reduce the muxed read signals
527 # for unary-addressed
528 comb
+= rport
.ren
.eq(ortreereduce_sig(rens
))
530 # for binary-addressed
531 comb
+= rport
.addr
.eq(ortreereduce_sig(addrs
))
532 comb
+= rport
.ren
.eq(Cat(*rens
).bool())
533 print ("binary", regfile
, rpidx
, rport
, rport
.ren
, rens
, addrs
)
535 if not self
.make_hazard_vecs
:
536 return Const(0) # declare "no hazards"
538 # enable the read bitvectors for this issued instruction
539 # and return whether any write-hazard bit is set
540 comb
+= wvchk
.ren
.eq(ortreereduce_sig(wvens
))
541 hazard_detected
= Signal(name
="raw_%s_%s" % (regfile
, rpidx
))
542 comb
+= hazard_detected
.eq(wvchk
.o_data
.bool())
543 return hazard_detected
545 def connect_rdports(self
, m
, fu_bitdict
):
546 """connect read ports
548 orders the read regspecs into a dict-of-dicts, by regfile, by
549 regport name, then connects all FUs that want that regport by
550 way of a PriorityPicker.
552 comb
, sync
= m
.d
.comb
, m
.d
.sync
557 # dictionary of lists of regfile read ports
558 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
560 # okaay, now we need a PriorityPicker per regfile per regfile port
561 # loootta pickers... peter piper picked a pack of pickled peppers...
563 for regfile
, spec
in byregfiles_rd
.items():
564 fuspecs
= byregfiles_rdspec
[regfile
]
565 rdpickers
[regfile
] = {}
567 # argh. an experiment to merge RA and RB in the INT regfile
568 # (we have too many read/write ports)
569 if self
.regreduce_en
:
571 fuspecs
['rabc'] = [fuspecs
.pop('rb')]
572 fuspecs
['rabc'].append(fuspecs
.pop('rc'))
573 fuspecs
['rabc'].append(fuspecs
.pop('ra'))
574 if regfile
== 'FAST':
575 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
576 if 'fast2' in fuspecs
:
577 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
578 if 'fast3' in fuspecs
:
579 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
581 # for each named regfile port, connect up all FUs to that port
582 # also return (and collate) hazard detection)
583 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
584 print("connect rd", regname
, fspec
)
585 rh
= self
.connect_rdport(m
, fu_bitdict
, rdpickers
, regfile
,
589 return Cat(*rd_hazard
).bool()
591 def make_hazards(self
, m
, regfile
, rfile
, wvclr
, wvset
,
592 funame
, regname
, idx
,
593 addr_en
, wp
, fu
, fu_active
, wrflag
, write
,
595 """make_hazards: a setter and a clearer for the regfile write ports
597 setter is at issue time (using PowerDecoder2 regfile write numbers)
598 clearer is at regfile write time (when FU has said what to write to)
600 there is *one* unusual case here which has to be dealt with:
601 when the Function Unit does *NOT* request a write to the regfile
602 (has its data.ok bit CLEARED). this is perfectly legitimate.
605 comb
, sync
= m
.d
.comb
, m
.d
.sync
606 name
= "%s_%s_%d" % (funame
, regname
, idx
)
608 # connect up the bitvector write hazard. unlike the
609 # regfile writeports, a ONE must be written to the corresponding
610 # bit of the hazard bitvector (to indicate the existence of
613 # the detection of what shall be written to is based
615 print ("write vector (for regread)", regfile
, wvset
)
616 wviaddr_en
= Signal(len(wvset
.wen
), name
="wv_issue_addr_en_"+name
)
617 issue_active
= Signal(name
="iactive_"+name
)
618 comb
+= issue_active
.eq(fu
.issue_i
& fu_active
& wrflag
)
619 with m
.If(issue_active
):
621 comb
+= wviaddr_en
.eq(write
)
623 comb
+= wviaddr_en
.eq(1<<write
)
625 # deal with write vector clear: this kicks in when the regfile
626 # is written to, and clears the corresponding bitvector entry
627 print ("write vector", regfile
, wvclr
)
628 wvaddr_en
= Signal(len(wvclr
.wen
), name
="wvaddr_en_"+name
)
630 comb
+= wvaddr_en
.eq(addr_en
)
633 comb
+= wvaddr_en
.eq(1<<addr_en
)
635 # XXX ASSUME that LDSTFunctionUnit always sets the data it intends to
636 # this may NOT be the case when an exception occurs
637 if isinstance(fu
, LDSTFunctionUnit
):
638 return wvaddr_en
, wviaddr_en
640 # okaaay, this is preparation for the awkward case.
641 # * latch a copy of wrflag when issue goes high.
642 # * when the fu_wrok (data.ok) flag is NOT set,
643 # but the FU is done, the FU is NEVER going to write
644 # so the bitvector has to be cleared.
645 latch_wrflag
= Signal(name
="latch_wrflag_"+name
)
646 with m
.If(~fu
.busy_o
):
647 sync
+= latch_wrflag
.eq(0)
648 with m
.If(fu
.issue_i
& fu_active
):
649 sync
+= latch_wrflag
.eq(wrflag
)
650 with m
.If(fu
.alu_done_o
& latch_wrflag
& ~fu_wrok
):
652 comb
+= wvaddr_en
.eq(write
) # addr_en gated with wp, don't use
654 comb
+= wvaddr_en
.eq(1<<addr_en
) # binary addr_en not gated
656 return wvaddr_en
, wviaddr_en
658 def connect_wrport(self
, m
, fu_bitdict
, wrpickers
, regfile
, regname
, fspec
):
659 comb
, sync
= m
.d
.comb
, m
.d
.sync
665 # select the required write port. these are pre-defined sizes
666 rfile
= regs
.rf
[regfile
.lower()]
667 wport
= rfile
.w_ports
[rpidx
]
669 print("connect wr", regname
, "unary", rfile
.unary
, fspec
)
670 print(regfile
, regs
.rf
.keys())
672 # select the write-protection hazard vector. note that this still
673 # requires to WRITE to the hazard bitvector! read-requests need
674 # to RAISE the bitvector (set it to 1), which, duh, requires a WRITE
675 if self
.make_hazard_vecs
:
676 wv
= regs
.wv
[regfile
.lower()]
677 wvset
= wv
.w_ports
["set"] # write-vec bit-level hazard ctrl
678 wvclr
= wv
.w_ports
["clr"] # write-vec bit-level hazard ctrl
681 if not isinstance(fspecs
, list):
689 for i
, fspec
in enumerate(fspecs
):
690 # get the regfile specs for this regfile port
691 (rf
, wf
, read
, write
, wid
, fuspec
) = fspec
692 print ("fpsec", i
, "wrflag", wf
, fspec
, len(fuspec
))
693 ppoffs
.append(pplen
) # record offset for picker
696 name
= "%s_%s_%d" % (regfile
, regname
, i
)
697 rdflag
= Signal(name
="rd_flag_"+name
)
698 wrflag
= Signal(name
="wr_flag_"+name
)
700 comb
+= rdflag
.eq(rf
)
704 comb
+= wrflag
.eq(wf
)
707 rdflags
.append(rdflag
)
708 wrflags
.append(wrflag
)
710 # create a priority picker to manage this port
711 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(pplen
)
712 setattr(m
.submodules
, "wrpick_%s_%s" % (regfile
, rpidx
), wrpick
)
720 for i
, fspec
in enumerate(fspecs
):
721 # connect up the FU req/go signals and the reg-read to the FU
722 # these are arbitrated by Data.ok signals
723 (rf
, wf
, read
, _write
, wid
, fuspec
) = fspec
724 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
726 name
= "%s_%s_%s_%d" % (funame
, regfile
, regname
, idx
)
727 # get (or set up) a write-latched copy of write register number
728 write
= Signal
.like(_write
, name
="write_"+name
)
729 rname
= "%s_%s_%s" % (funame
, regfile
, regname
)
730 if rname
not in fu
.wr_latches
:
731 wrl
= Signal
.like(_write
, name
="wrlatch_"+rname
)
732 fu
.wr_latches
[rname
] = write
733 with m
.If(fu
.issue_i
):
734 sync
+= wrl
.eq(_write
)
735 comb
+= write
.eq(_write
)
737 comb
+= write
.eq(wrl
)
739 write
= fu
.wr_latches
[rname
]
741 # write-request comes from dest.ok
742 dest
= fu
.get_out(idx
)
743 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
744 name
= "fu_wrok_%s_%s_%d" % (funame
, regname
, idx
)
745 fu_wrok
= Signal(name
=name
, reset_less
=True)
746 comb
+= fu_wrok
.eq(dest
.ok
& fu
.busy_o
)
748 # connect request-write to picker input, and output to go-wr
749 fu_active
= fu_bitdict
[funame
]
750 pick
= fu
.wr
.rel_o
[idx
] & fu_active
751 comb
+= wrpick
.i
[pi
].eq(pick
)
752 # create a single-pulse go write from the picker output
753 wr_pick
= Signal(name
="wpick_%s_%s_%d" % (funame
, regname
, idx
))
754 comb
+= wr_pick
.eq(wrpick
.o
[pi
] & wrpick
.en_o
)
755 comb
+= fu
.go_wr_i
[idx
].eq(rising_edge(m
, wr_pick
))
757 # connect the regspec write "reg select" number to this port
758 # only if one FU actually requests (and is granted) the port
759 # will the write-enable be activated
760 wname
= "waddr_en_%s_%s_%d" % (funame
, regname
, idx
)
761 addr_en
= Signal
.like(write
, name
=wname
)
763 comb
+= wp
.eq(wr_pick
& wrpick
.en_o
)
764 comb
+= addr_en
.eq(Mux(wp
, write
, 0))
768 addrs
.append(addr_en
)
771 # connect regfile port to input
772 print("reg connect widths",
773 regfile
, regname
, pi
, funame
,
774 dest
.shape(), wport
.i_data
.shape())
775 wsigs
.append(fu_dest_latch
)
777 # now connect up the bitvector write hazard
778 if not self
.make_hazard_vecs
:
780 res
= self
.make_hazards(m
, regfile
, rfile
, wvclr
, wvset
,
781 funame
, regname
, idx
,
782 addr_en
, wp
, fu
, fu_active
,
783 wrflags
[i
], write
, fu_wrok
)
784 wvaddr_en
, wv_issue_en
= res
785 wvclren
.append(wvaddr_en
) # set only: no data => clear bit
786 wvseten
.append(wv_issue_en
) # set data same as enable
787 wvsets
.append(wv_issue_en
) # because enable needs a 1
789 # here is where we create the Write Broadcast Bus. simple, eh?
790 comb
+= wport
.i_data
.eq(ortreereduce_sig(wsigs
))
792 # for unary-addressed
793 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
795 # for binary-addressed
796 comb
+= wport
.addr
.eq(ortreereduce_sig(addrs
))
797 comb
+= wport
.wen
.eq(ortreereduce_sig(wens
))
799 if not self
.make_hazard_vecs
:
803 comb
+= wvclr
.wen
.eq(ortreereduce_sig(wvclren
)) # clear (regfile write)
804 comb
+= wvset
.wen
.eq(ortreereduce_sig(wvseten
)) # set (issue time)
805 comb
+= wvset
.i_data
.eq(ortreereduce_sig(wvsets
))
807 def connect_wrports(self
, m
, fu_bitdict
):
808 """connect write ports
810 orders the write regspecs into a dict-of-dicts, by regfile,
811 by regport name, then connects all FUs that want that regport
812 by way of a PriorityPicker.
814 note that the write-port wen, write-port data, and go_wr_i all need to
815 be on the exact same clock cycle. as there is a combinatorial loop bug
816 at the moment, these all use sync.
818 comb
, sync
= m
.d
.comb
, m
.d
.sync
821 # dictionary of lists of regfile write ports
822 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
824 # same for write ports.
825 # BLECH! complex code-duplication! BLECH!
827 for regfile
, spec
in byregfiles_wr
.items():
828 fuspecs
= byregfiles_wrspec
[regfile
]
829 wrpickers
[regfile
] = {}
831 if self
.regreduce_en
:
832 # argh, more port-merging
834 fuspecs
['o'] = [fuspecs
.pop('o')]
835 fuspecs
['o'].append(fuspecs
.pop('o1'))
836 if regfile
== 'FAST':
837 fuspecs
['fast1'] = [fuspecs
.pop('fast1')]
838 if 'fast2' in fuspecs
:
839 fuspecs
['fast1'].append(fuspecs
.pop('fast2'))
840 if 'fast3' in fuspecs
:
841 fuspecs
['fast1'].append(fuspecs
.pop('fast3'))
843 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
844 self
.connect_wrport(m
, fu_bitdict
, wrpickers
,
845 regfile
, regname
, fspec
)
847 def get_byregfiles(self
, readmode
):
849 mode
= "read" if readmode
else "write"
852 e
= self
.ireg
.e
# decoded instruction to execute
854 # dictionary of dictionaries of lists of regfile ports.
855 # first key: regfile. second key: regfile port name
856 byregfiles
= defaultdict(dict)
857 byregfiles_spec
= defaultdict(dict)
859 for (funame
, fu
) in fus
.items():
860 # create in each FU a receptacle for the read/write register
861 # hazard numbers. to be latched in connect_rd/write_ports
862 # XXX better that this is moved into the actual FUs, but
863 # the issue there is that this function is actually better
864 # suited at the moment
870 print("%s ports for %s" % (mode
, funame
))
871 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
872 # construct regfile specs: read uses inspec, write outspec
874 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
876 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
877 print(" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
879 # the PowerDecoder2 (main one, not the satellites) contains
880 # the decoded regfile numbers. obtain these now
882 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
883 wrport
, write
= None, None
885 rdflag
, read
= None, None
886 wrport
, write
= regspec_decode_write(e
, regfile
, regname
)
888 # construct the dictionary of regspec information by regfile
889 if regname
not in byregfiles_spec
[regfile
]:
890 byregfiles_spec
[regfile
][regname
] = \
891 (rdflag
, wrport
, read
, write
, wid
, [])
892 # here we start to create "lanes"
893 if idx
not in byregfiles
[regfile
]:
894 byregfiles
[regfile
][idx
] = []
895 fuspec
= (funame
, fu
, idx
)
896 byregfiles
[regfile
][idx
].append(fuspec
)
897 byregfiles_spec
[regfile
][regname
][5].append(fuspec
)
900 # append a latch Signal to the FU's list of latches
901 rname
= "%s_%s" % (regfile
, regname
)
903 if rname
not in fu
.rd_latches
:
904 rdl
= Signal
.like(read
, name
="rdlatch_"+rname
)
905 fu
.rd_latches
[rname
] = rdl
907 if rname
not in fu
.wr_latches
:
908 wrl
= Signal
.like(write
, name
="wrlatch_"+rname
)
909 fu
.wr_latches
[rname
] = wrl
911 # ok just print that all out, for convenience
912 for regfile
, spec
in byregfiles
.items():
913 print("regfile %s ports:" % mode
, regfile
)
914 fuspecs
= byregfiles_spec
[regfile
]
915 for regname
, fspec
in fuspecs
.items():
916 [rdflag
, wrflag
, read
, write
, wid
, fuspec
] = fspec
917 print(" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
918 print(" %s" % regname
, wid
, read
, write
, rdflag
, wrflag
)
919 for (funame
, fu
, idx
) in fuspec
:
920 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
921 print(" ", funame
, fu
.__class
__.__name
__, idx
, fusig
)
924 return byregfiles
, byregfiles_spec
927 yield from self
.fus
.ports()
928 yield from self
.i
.e
.ports()
929 yield from self
.l0
.ports()
936 if __name__
== '__main__':
937 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
942 dut
= NonProductionCore(pspec
)
943 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
944 with
open("test_core.il", "w") as f
: