src/soc/simple/core.py

   1 """simple core
   2
   3 not in any way intended for production use.  connects up FunctionUnits to
   4 Register Files in a brain-dead fashion that only permits one and only one
   5 Function Unit to be operational.
   6
   7 the principle here is to take the Function Units, analyse their regspecs,
   8 and turn their requirements for access to register file read/write ports
   9 into groupings by Register File and Register File Port name.
  10
  11 under each grouping - by regfile/port - a list of Function Units that
  12 need to connect to that port is created.  as these are a contended
  13 resource a "Broadcast Bus" per read/write port is then also created,
  14 with access to it managed by a PriorityPicker.
  15
  16 the brain-dead part of this module is that even though there is no
  17 conflict of access, regfile read/write hazards are *not* analysed,
  18 and consequently it is safer to wait for the Function Unit to complete
  19 before allowing a new instruction to proceed.
  20 """
  21
  22 from nmigen import Elaboratable, Module, Signal, ResetSignal
  23 from nmigen.cli import rtlil
  24
  25 from nmutil.picker import PriorityPicker
  26 from nmutil.util import treereduce
  27
  28 from soc.fu.compunits.compunits import AllFunctionUnits
  29 from soc.regfile.regfiles import RegFiles
  30 from soc.decoder.power_decoder import create_pdecode
  31 from soc.decoder.power_decoder2 import PowerDecode2
  32 from soc.decoder.decode2execute1 import Data
  33 from soc.experiment.l0_cache import TstL0CacheBuffer  # test only
  34 from soc.config.test.test_loadstore import TestMemPspec
  35 from soc.decoder.power_enums import MicrOp
  36 import operator
  37
  38
  39 # helper function for reducing a list of signals down to a parallel
  40 # ORed single signal.
  41 def ortreereduce(tree, attr="data_o"):
  42     return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
  43
  44
  45 def ortreereduce_sig(tree):
  46     return treereduce(tree, operator.or_, lambda x: x)
  47
  48
  49 # helper function to place full regs declarations first
  50 def sort_fuspecs(fuspecs):
  51     res = []
  52     for (regname, fspec) in fuspecs.items():
  53         if regname.startswith("full"):
  54             res.append((regname, fspec))
  55     for (regname, fspec) in fuspecs.items():
  56         if not regname.startswith("full"):
  57             res.append((regname, fspec))
  58     return res  # enumerate(res)
  59
  60
  61 class NonProductionCore(Elaboratable):
  62     def __init__(self, pspec):
  63         # single LD/ST funnel for memory access
  64         self.l0 = TstL0CacheBuffer(pspec, n_units=1)
  65         pi = self.l0.l0.dports[0]
  66
  67         # function units (only one each)
  68         self.fus = AllFunctionUnits(pspec, pilist=[pi])
  69
  70         # register files (yes plural)
  71         self.regs = RegFiles()
  72
  73         # instruction decoder
  74         pdecode = create_pdecode()
  75         self.pdecode2 = PowerDecode2(pdecode)   # instruction decoder
  76
  77         # issue/valid/busy signalling
  78         self.ivalid_i = self.pdecode2.valid   # instruction is valid
  79         self.issue_i = Signal(reset_less=True)
  80         self.busy_o = Signal(name="corebusy_o", reset_less=True)
  81
  82         # instruction input
  83         self.bigendian_i = self.pdecode2.dec.bigendian
  84         self.raw_opcode_i = self.pdecode2.dec.raw_opcode_in
  85
  86         # start/stop and terminated signalling
  87         self.core_stopped_i = Signal(reset_less=True)
  88         self.core_reset_i = Signal()
  89         self.core_terminate_o = Signal(reset=0)  # indicates stopped
  90
  91     def elaborate(self, platform):
  92         m = Module()
  93
  94         m.submodules.pdecode2 = dec2 = self.pdecode2
  95         m.submodules.fus = self.fus
  96         m.submodules.l0 = l0 = self.l0
  97         self.regs.elaborate_into(m, platform)
  98         regs = self.regs
  99         fus = self.fus.fus
 100
 101         # connect up Function Units, then read/write ports
 102         fu_bitdict = self.connect_instruction(m)
 103         self.connect_rdports(m, fu_bitdict)
 104         self.connect_wrports(m, fu_bitdict)
 105
 106         # connect up reset
 107         m.d.comb += ResetSignal().eq(self.core_reset_i)
 108
 109         return m
 110
 111     def connect_instruction(self, m):
 112         """connect_instruction
 113
 114         uses decoded (from PowerOp) function unit information from CSV files
 115         to ascertain which Function Unit should deal with the current
 116         instruction.
 117
 118         some (such as OP_ATTN, OP_NOP) are dealt with here, including
 119         ignoring it and halting the processor.  OP_NOP is a bit annoying
 120         because the issuer expects busy flag still to be raised then lowered.
 121         (this requires a fake counter to be set).
 122         """
 123         comb, sync = m.d.comb, m.d.sync
 124         fus = self.fus.fus
 125         dec2 = self.pdecode2
 126
 127         # enable-signals for each FU, get one bit for each FU (by name)
 128         fu_enable = Signal(len(fus), reset_less=True)
 129         fu_bitdict = {}
 130         for i, funame in enumerate(fus.keys()):
 131             fu_bitdict[funame] = fu_enable[i]
 132
 133         # enable the required Function Unit based on the opcode decode
 134         # note: this *only* works correctly for simple core when one and
 135         # *only* one FU is allocated per instruction
 136         for funame, fu in fus.items():
 137             fnunit = fu.fnunit.value
 138             enable = Signal(name="en_%s" % funame, reset_less=True)
 139             comb += enable.eq((dec2.e.do.fn_unit & fnunit).bool())
 140             comb += fu_bitdict[funame].eq(enable)
 141
 142         # sigh - need a NOP counter
 143         counter = Signal(2)
 144         with m.If(counter != 0):
 145             sync += counter.eq(counter - 1)
 146             comb += self.busy_o.eq(1)
 147
 148         with m.If(self.ivalid_i): # run only when valid
 149             with m.Switch(dec2.e.do.insn_type):
 150                 # check for ATTN: halt if true
 151                 with m.Case(MicrOp.OP_ATTN):
 152                     m.d.sync += self.core_terminate_o.eq(1)
 153
 154                 with m.Case(MicrOp.OP_NOP):
 155                     sync += counter.eq(2)
 156                     comb += self.busy_o.eq(1)
 157
 158                 with m.Default():
 159                     # connect up instructions.  only one enabled at a time
 160                     for funame, fu in fus.items():
 161                         enable = fu_bitdict[funame]
 162
 163                         # run this FunctionUnit if enabled
 164                         with m.If(enable):
 165                             # route op, issue, busy, read flags and mask to FU
 166                             comb += fu.oper_i.eq_from_execute1(dec2.e)
 167                             comb += fu.issue_i.eq(self.issue_i)
 168                             comb += self.busy_o.eq(fu.busy_o)
 169                             rdmask = dec2.rdflags(fu)
 170                             comb += fu.rdmaskn.eq(~rdmask)
 171
 172         return fu_bitdict
 173
 174     def connect_rdports(self, m, fu_bitdict):
 175         """connect read ports
 176
 177         orders the read regspecs into a dict-of-dicts, by regfile, by
 178         regport name, then connects all FUs that want that regport by
 179         way of a PriorityPicker.
 180         """
 181         comb, sync = m.d.comb, m.d.sync
 182         fus = self.fus.fus
 183         regs = self.regs
 184
 185         # dictionary of lists of regfile read ports
 186         byregfiles_rd, byregfiles_rdspec = self.get_byregfiles(True)
 187
 188         # okaay, now we need a PriorityPicker per regfile per regfile port
 189         # loootta pickers... peter piper picked a pack of pickled peppers...
 190         rdpickers = {}
 191         for regfile, spec in byregfiles_rd.items():
 192             fuspecs = byregfiles_rdspec[regfile]
 193             rdpickers[regfile] = {}
 194
 195             # for each named regfile port, connect up all FUs to that port
 196             for (regname, fspec) in sort_fuspecs(fuspecs):
 197                 print("connect rd", regname, fspec)
 198                 rpidx = regname
 199                 # get the regfile specs for this regfile port
 200                 (rf, read, write, wid, fuspec) = fspec
 201                 name = "rdflag_%s_%s" % (regfile, regname)
 202                 rdflag = Signal(name=name, reset_less=True)
 203                 comb += rdflag.eq(rf)
 204
 205                 # select the required read port.  these are pre-defined sizes
 206                 print(rpidx, regfile, regs.rf.keys())
 207                 rport = regs.rf[regfile.lower()].r_ports[rpidx]
 208
 209                 # create a priority picker to manage this port
 210                 rdpickers[regfile][rpidx] = rdpick = PriorityPicker(
 211                     len(fuspec))
 212                 setattr(m.submodules, "rdpick_%s_%s" %
 213                         (regfile, rpidx), rdpick)
 214
 215                 # connect the regspec "reg select" number to this port
 216                 with m.If(rdpick.en_o):
 217                     comb += rport.ren.eq(read)
 218
 219                 # connect up the FU req/go signals, and the reg-read to the FU
 220                 # and create a Read Broadcast Bus
 221                 for pi, (funame, fu, idx) in enumerate(fuspec):
 222                     src = fu.src_i[idx]
 223
 224                     # connect request-read to picker input, and output to go-rd
 225                     fu_active = fu_bitdict[funame]
 226                     pick = fu.rd_rel_o[idx] & fu_active & rdflag
 227                     comb += rdpick.i[pi].eq(pick)
 228                     comb += fu.go_rd_i[idx].eq(rdpick.o[pi])
 229
 230                     # connect regfile port to input, creating a Broadcast Bus
 231                     print("reg connect widths",
 232                           regfile, regname, pi, funame,
 233                           src.shape(), rport.data_o.shape())
 234                     # all FUs connect to same port
 235                     comb += src.eq(rport.data_o)
 236
 237     def connect_wrports(self, m, fu_bitdict):
 238         """connect write ports
 239
 240         orders the write regspecs into a dict-of-dicts, by regfile,
 241         by regport name, then connects all FUs that want that regport
 242         by way of a PriorityPicker.
 243
 244         note that the write-port wen, write-port data, and go_wr_i all need to
 245         be on the exact same clock cycle.  as there is a combinatorial loop bug
 246         at the moment, these all use sync.
 247         """
 248         comb, sync = m.d.comb, m.d.sync
 249         fus = self.fus.fus
 250         regs = self.regs
 251         # dictionary of lists of regfile write ports
 252         byregfiles_wr, byregfiles_wrspec = self.get_byregfiles(False)
 253
 254         # same for write ports.
 255         # BLECH!  complex code-duplication! BLECH!
 256         wrpickers = {}
 257         for regfile, spec in byregfiles_wr.items():
 258             fuspecs = byregfiles_wrspec[regfile]
 259             wrpickers[regfile] = {}
 260             for (regname, fspec) in sort_fuspecs(fuspecs):
 261                 print("connect wr", regname, fspec)
 262                 rpidx = regname
 263                 # get the regfile specs for this regfile port
 264                 (rf, read, write, wid, fuspec) = fspec
 265
 266                 # select the required write port.  these are pre-defined sizes
 267                 print(regfile, regs.rf.keys())
 268                 wport = regs.rf[regfile.lower()].w_ports[rpidx]
 269
 270                 # create a priority picker to manage this port
 271                 wrpickers[regfile][rpidx] = wrpick = PriorityPicker(
 272                     len(fuspec))
 273                 setattr(m.submodules, "wrpick_%s_%s" %
 274                         (regfile, rpidx), wrpick)
 275
 276                 # connect the regspec write "reg select" number to this port
 277                 # only if one FU actually requests (and is granted) the port
 278                 # will the write-enable be activated
 279                 with m.If(wrpick.en_o):
 280                     comb += wport.wen.eq(write)
 281                 with m.Else():
 282                     comb += wport.wen.eq(0)
 283
 284                 # connect up the FU req/go signals and the reg-read to the FU
 285                 # these are arbitrated by Data.ok signals
 286                 wsigs = []
 287                 for pi, (funame, fu, idx) in enumerate(fuspec):
 288                     # write-request comes from dest.ok
 289                     dest = fu.get_out(idx)
 290                     fu_dest_latch = fu.get_fu_out(idx)  # latched output
 291                     name = "wrflag_%s_%s_%d" % (funame, regname, idx)
 292                     wrflag = Signal(name=name, reset_less=True)
 293                     comb += wrflag.eq(dest.ok & fu.busy_o)
 294
 295                     # connect request-read to picker input, and output to go-wr
 296                     fu_active = fu_bitdict[funame]
 297                     pick = fu.wr.rel_o[idx] & fu_active  # & wrflag
 298                     comb += wrpick.i[pi].eq(pick)
 299                     comb += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o)
 300                     # connect regfile port to input
 301                     print("reg connect widths",
 302                           regfile, regname, pi, funame,
 303                           dest.shape(), wport.data_i.shape())
 304                     wsigs.append(fu_dest_latch)
 305
 306                 # here is where we create the Write Broadcast Bus. simple, eh?
 307                 comb += wport.data_i.eq(ortreereduce_sig(wsigs))
 308
 309     def get_byregfiles(self, readmode):
 310
 311         mode = "read" if readmode else "write"
 312         dec2 = self.pdecode2
 313         regs = self.regs
 314         fus = self.fus.fus
 315
 316         # dictionary of lists of regfile ports
 317         byregfiles = {}
 318         byregfiles_spec = {}
 319         for (funame, fu) in fus.items():
 320             print("%s ports for %s" % (mode, funame))
 321             for idx in range(fu.n_src if readmode else fu.n_dst):
 322                 if readmode:
 323                     (regfile, regname, wid) = fu.get_in_spec(idx)
 324                 else:
 325                     (regfile, regname, wid) = fu.get_out_spec(idx)
 326                 print("    %d %s %s %s" % (idx, regfile, regname, str(wid)))
 327                 if readmode:
 328                     rdflag, read = dec2.regspecmap_read(regfile, regname)
 329                     write = None
 330                 else:
 331                     rdflag, read = None, None
 332                     wrport, write = dec2.regspecmap_write(regfile, regname)
 333                 if regfile not in byregfiles:
 334                     byregfiles[regfile] = {}
 335                     byregfiles_spec[regfile] = {}
 336                 if regname not in byregfiles_spec[regfile]:
 337                     byregfiles_spec[regfile][regname] = \
 338                         [rdflag, read, write, wid, []]
 339                 # here we start to create "lanes"
 340                 if idx not in byregfiles[regfile]:
 341                     byregfiles[regfile][idx] = []
 342                 fuspec = (funame, fu, idx)
 343                 byregfiles[regfile][idx].append(fuspec)
 344                 byregfiles_spec[regfile][regname][4].append(fuspec)
 345
 346         # ok just print that out, for convenience
 347         for regfile, spec in byregfiles.items():
 348             print("regfile %s ports:" % mode, regfile)
 349             fuspecs = byregfiles_spec[regfile]
 350             for regname, fspec in fuspecs.items():
 351                 [rdflag, read, write, wid, fuspec] = fspec
 352                 print("  rf %s port %s lane: %s" % (mode, regfile, regname))
 353                 print("  %s" % regname, wid, read, write, rdflag)
 354                 for (funame, fu, idx) in fuspec:
 355                     fusig = fu.src_i[idx] if readmode else fu.dest[idx]
 356                     print("    ", funame, fu, idx, fusig)
 357                     print()
 358
 359         return byregfiles, byregfiles_spec
 360
 361     def __iter__(self):
 362         yield from self.fus.ports()
 363         yield from self.pdecode2.ports()
 364         yield from self.l0.ports()
 365         # TODO: regs
 366
 367     def ports(self):
 368         return list(self)
 369
 370
 371 if __name__ == '__main__':
 372     pspec = TestMemPspec(ldst_ifacetype='testpi',
 373                          imem_ifacetype='',
 374                          addr_wid=48,
 375                          mask_wid=8,
 376                          reg_wid=64)
 377     dut = NonProductionCore(pspec)
 378     vl = rtlil.convert(dut, ports=dut.ports())
 379     with open("test_core.il", "w") as f:
 380         f.write(vl)