src/spec/dmi_sim.py

   1 """DMI "simulator" process for nmigen tests
   2 """
   3
   4 from dmi import  DBGCore, DBGCtrl, DBGStat
   5
   6 def dmi_sim(dut):
   7
   8     ctrl_reg = 0b100 # terminated
   9
  10     dmi = dut.dmi
  11     while not dut.stop:
  12         # wait for req
  13         req = yield dmi.req_i
  14         if req == 0:
  15             yield
  16             continue
  17
  18         # check read/write and address
  19         wen = yield dmi.we_i
  20         addr = yield dmi.addr_i
  21         print ("        dmi wen, addr", wen, addr)
  22
  23         # Control read
  24         if addr == DBGCore.CTRL and wen == 0:
  25             print ("        read ctrl reg", ctrl_reg)
  26             yield dmi.dout.eq(ctrl_reg)
  27             yield dmi.ack_o.eq(1)
  28             yield
  29             yield dmi.ack_o.eq(0)
  30
  31         # Control write
  32         elif addr == DBGCore.CTRL and wen == 1:
  33             stat = (yield dmi.din)
  34             if (stat & (1<<DBGCtrl.STOP)):
  35                 ctrl_reg |= (1<<DBGStat.STOPPED)
  36                 ctrl_reg &= ~(1<<DBGStat.STOPPING)
  37             if (stat & (1<<DBGCtrl.START)):
  38                 ctrl_reg = 0
  39             print ("        write ctrl reg", stat, ctrl_reg)
  40             yield dmi.ack_o.eq(1)
  41             yield
  42             yield dmi.ack_o.eq(0)
  43
  44         # allow MSR write
  45         elif addr == DBGCore.MSR and wen == 0:
  46             print ("        read msr reg")
  47             yield dmi.dout.eq(0xdeadbeef) # test MSR value
  48             yield dmi.ack_o.eq(1)
  49             yield
  50             yield dmi.ack_o.eq(0)
  51         else:
  52             # do nothing but just ack it
  53             yield dmi.ack_o.eq(1)
  54             yield
  55             yield dmi.ack_o.eq(0)
  56
  57     print ("dmi sim stopping")