1 """DMI "simulator" process for nmigen tests
4 from dmi
import DBGCore
, DBGCtrl
, DBGStat
8 ctrl_reg
= 0b100 # terminated
18 # check read/write and address
20 addr
= yield dmi
.addr_i
21 print (" dmi wen, addr", wen
, addr
)
24 if addr
== DBGCore
.CTRL
and wen
== 0:
25 print (" read ctrl reg", ctrl_reg
)
26 yield dmi
.dout
.eq(ctrl_reg
)
32 elif addr
== DBGCore
.CTRL
and wen
== 1:
33 stat
= (yield dmi
.din
)
34 if (stat
& (1<<DBGCtrl
.STOP
)):
35 ctrl_reg |
= (1<<DBGStat
.STOPPED
)
36 ctrl_reg
&= ~
(1<<DBGStat
.STOPPING
)
37 if (stat
& (1<<DBGCtrl
.START
)):
39 print (" write ctrl reg", stat
, ctrl_reg
)
45 elif addr
== DBGCore
.MSR
and wen
== 0:
46 print (" read msr reg")
47 yield dmi
.dout
.eq(0xdeadbeef) # test MSR value
52 # do nothing but just ack it
57 print ("dmi sim stopping")