3 from copy
import deepcopy
6 def namesuffix(name
, suffix
, namelist
):
10 names
.append("%s%s_%s" % (name
, suffix
, n
))
12 names
.append("%s_%s" % (name
, suffix
))
16 class Pinouts(object):
17 def __init__(self
, bankspec
):
18 self
.bankspec
= bankspec
22 def __contains__(self
, k
):
28 def add_spec(self
, k
, v
):
31 def update(self
, pinidx
, v
):
32 if pinidx
not in self
.pins
:
35 self
.pins
[pinidx
].update(v
)
38 return self
.pins
.keys()
41 return self
.pins
.items()
49 def __delitem__(self
, k
):
52 def __getitem__(self
, k
):
55 def i2s(self
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
56 i2spins
= ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+']
58 # i2spins.append("DO%d+" % i)
59 pins
= Pins('IIS', i2spins
, self
.bankspec
,
60 suffix
, offs
, bank
, mux
,
61 spec
, limit
, origsuffix
=suffix
)
64 def emmc(self
, suffix
, offs
, bank
, mux
=1, spec
=None):
65 emmcpins
= ['CMD+', 'CLK+']
67 emmcpins
.append("D%d*" % i
)
68 pins
= Pins('MMC', emmcpins
, self
.bankspec
,
69 suffix
, offs
, bank
, mux
,
70 spec
, origsuffix
=suffix
)
73 def sdmmc(self
, suffix
, offs
, bank
, mux
=1, spec
=None,
74 start
=None, limit
=None):
75 sdmmcpins
= ['CMD+', 'CLK+']
77 sdmmcpins
.append("D%d*" % i
)
78 sdmmcpins
= sdmmcpins
[start
:limit
]
79 pins
= Pins('SD', sdmmcpins
, self
.bankspec
,
80 suffix
, offs
, bank
, mux
,
81 spec
, origsuffix
=suffix
)
84 def spi(self
, suffix
, offs
, bank
, mux
=1, spec
=None):
85 spipins
= ['CLK*', 'NSS*', 'MOSI*', 'MISO*']
86 pins
= Pins('SPI', spipins
, self
.bankspec
,
87 suffix
, offs
, bank
, mux
,
88 spec
, origsuffix
=suffix
)
91 def quadspi(self
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
92 spipins
= ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*']
93 pins
= Pins('QSPI', spipins
, self
.bankspec
,
94 suffix
, offs
, bank
, mux
,
95 spec
, limit
, origsuffix
=suffix
)
98 def i2c(self
, suffix
, offs
, bank
, mux
=1, spec
=None):
99 spipins
= ['SDA*', 'SCL*']
100 pins
= Pins('TWI', spipins
, self
.bankspec
,
101 suffix
, offs
, bank
, mux
,
102 spec
, origsuffix
=suffix
)
105 def jtag(self
, suffix
, offs
, bank
, mux
=1, spec
=None):
106 jtagpins
= ['MS+', 'DI-', 'DO+', 'CK+']
107 pins
= Pins('JTAG', jtagpins
, self
.bankspec
,
108 suffix
, offs
, bank
, mux
,
109 spec
, origsuffix
=suffix
)
112 def uart(self
, suffix
, offs
, bank
, mux
=1, spec
=None):
113 uartpins
= ['TX+', 'RX-']
114 pins
= Pins('UART', uartpins
, self
.bankspec
,
115 suffix
, offs
, bank
, mux
,
116 spec
, origsuffix
=suffix
)
119 def ulpi(self
, suffix
, offs
, bank
, mux
=1, spec
=None):
120 ulpipins
= ['CK+', 'DIR+', 'STP+', 'NXT+']
122 ulpipins
.append('D%d*' % i
)
123 pins
= Pins('ULPI', ulpipins
, self
.bankspec
,
124 suffix
, offs
, bank
, mux
,
125 spec
, origsuffix
=suffix
)
128 def uartfull(self
, suffix
, offs
, bank
, mux
=1, spec
=None):
129 uartpins
= ['TX+', 'RX-', 'CTS-', 'RTS+']
130 pins
= Pins('UARTQ', uartpins
, self
.bankspec
,
131 suffix
, offs
, bank
, mux
,
132 spec
, origsuffix
=suffix
)
135 def rgbttl(self
, suffix
, offs
, bank
, mux
=1, spec
=None):
136 ttlpins
= ['CK+', 'DE+', 'HS+', 'VS+']
138 ttlpins
.append("D%d+" % i
)
139 pins
= Pins('LCD', ttlpins
, self
.bankspec
,
140 suffix
, offs
, bank
, mux
,
141 spec
, origsuffix
=suffix
)
144 def rgmii(self
, suffix
, offs
, bank
, mux
=1, spec
=None):
147 buspins
.append("ERXD%d-" % i
)
149 buspins
.append("ETXD%d+" % i
)
150 buspins
+= ['ERXCK-', 'ERXERR-', 'ERXDV-',
152 'ETXEN+', 'ETXCK+', 'ECRS-',
154 pins
= Pins('RG', buspins
, self
.bankspec
,
155 suffix
, offs
, bank
, mux
,
156 spec
, origsuffix
=suffix
)
159 def flexbus1(self
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
162 buspins
.append("AD%d*" % i
)
164 buspins
.append("CS%d+" % i
)
165 buspins
+= ['ALE', 'OE', 'RW', 'TA', 'CLK+',
166 'A0', 'A1', 'TS', 'TBST',
169 buspins
.append("BWE%d" % i
)
170 for i
in range(2, 6):
171 buspins
.append("CS%d+" % i
)
172 pins
= Pins('FB', buspins
, self
.bankspec
,
173 suffix
, offs
, bank
, mux
,
174 spec
, limit
, origsuffix
=suffix
)
177 def flexbus2(self
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
179 for i
in range(8, 32):
180 buspins
.append("AD%d*" % i
)
181 pins
= Pins('FB', buspins
, self
.bankspec
,
182 suffix
, offs
, bank
, mux
,
183 spec
, limit
, origsuffix
=suffix
)
186 def sdram1(self
, suffix
, offs
, bank
, mux
=1, spec
=None):
189 buspins
.append("SDRDQM%d*" % i
)
191 buspins
.append("SDRAD%d+" % i
)
193 buspins
.append("SDRDQ%d+" % i
)
195 buspins
.append("SDRCS%d#+" % i
)
197 buspins
.append("SDRDQ%d+" % i
)
199 buspins
.append("SDRBA%d+" % i
)
200 buspins
+= ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+',
202 pins
= Pins('SDR', buspins
, self
.bankspec
,
203 suffix
, offs
, bank
, mux
,
204 spec
, origsuffix
=suffix
)
207 def sdram2(self
, suffix
, offs
, bank
, mux
=1, spec
=None, limit
=None):
209 for i
in range(3, 6):
210 buspins
.append("SDRCS%d#+" % i
)
211 for i
in range(8, 32):
212 buspins
.append("SDRDQ%d*" % i
)
213 pins
= Pins('SDR', buspins
, self
.bankspec
,
214 suffix
, offs
, bank
, mux
,
215 spec
, limit
, origsuffix
=suffix
)
218 def mcu8080(self
, suffix
, offs
, bank
, mux
=1, spec
=None):
221 buspins
.append("MCUD%d*" % i
)
223 buspins
.append("MCUAD%d+" % (i
+ 8))
225 buspins
.append("MCUCS%d+" % i
)
227 buspins
.append("MCUNRB%d+" % i
)
228 buspins
+= ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+',
230 pins
= Pins('MCU', buspins
, self
.bankspec
,
231 suffix
, offs
, bank
, mux
,
232 spec
, origsuffix
=suffix
)
235 def _pinbank(self
, prefix
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1,
238 for i
in range(gpiooffs
, gpiooffs
+ gpionum
):
239 gpiopins
.append("%s%d*" % (bank
, i
))
240 pins
= Pins(prefix
, gpiopins
, self
.bankspec
,
241 suffix
, offs
, bank
, mux
,
242 spec
, origsuffix
=suffix
)
245 def eint(self
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
247 for i
in range(gpiooffs
, gpiooffs
+ gpionum
):
248 gpiopins
.append("%d*" % (i
))
249 pins
= Pins('EINT', gpiopins
, self
.bankspec
,
250 suffix
, offs
, bank
, mux
,
251 spec
, origsuffix
=suffix
)
254 def pwm(self
, suffix
, offs
, bank
, pwmoffs
, pwmnum
=1, mux
=1, spec
=None):
256 for i
in range(pwmoffs
, pwmoffs
+ pwmnum
):
257 pwmpins
.append("%d+" % (i
))
258 pins
= Pins('PWM', pwmpins
, self
.bankspec
,
259 suffix
, offs
, bank
, mux
,
260 spec
, origsuffix
=suffix
)
263 def gpio(self
, suffix
, offs
, bank
, gpiooffs
, gpionum
=1, mux
=1, spec
=None):
264 self
._pinbank
("GPIO%s" % bank
, suffix
, offs
, bank
, gpiooffs
,
265 gpionum
, mux
=0, spec
=None)
267 def pinmerge(self
, fn
):
268 # hack, store the function specs in the pins dict
270 suffix
= fn
.origsuffix
273 if not hasattr(self
, 'fnspec'):
277 assert 'EINT' not in self
278 if fname
not in self
.fnspec
:
279 self
.add_spec(fname
, {})
280 if suffix
or fname
== 'EINT' or fname
== 'PWM':
281 specname
= fname
+ suffix
284 #print "fname bank specname suffix ", fname, bank, specname, repr(
286 if specname
in self
.fnspec
[fname
]:
287 # ok so some declarations may bring in different
288 # names at different stages (EINT, PWM, flexbus1/2)
289 # so we have to merge the names in. main thing is
291 tomerge
= self
.fnspec
[fname
][specname
]
292 for p
in fn
.pingroup
:
293 if p
not in tomerge
.pingroup
:
294 tomerge
.pingroup
.append(p
)
295 tomerge
.pins
.update(fn
.pins
)
296 tomerge
.fntype
.update(fn
.fntype
)
298 self
.fnspec
[fname
][specname
] = deepcopy(fn
)
301 for (pinidx
, v
) in fn
.pins
.items():
302 self
.update(pinidx
, v
)
307 def __init__(self
, fname
, pingroup
, bankspec
, suffix
, offs
, bank
, mux
,
308 spec
=None, limit
=None, origsuffix
=None):
310 # function type can be in, out or inout, represented by - + *
311 # strip function type out of each pin name
313 for i
in range(len(pingroup
)):
318 if fntype
not in '+-*':
321 fntype
= {'-': 'in', '+': 'out', '*': 'inout'}[fntype
]
322 self
.fntype
[pname
] = fntype
326 self
.pingroup
= pingroup
327 self
.bankspec
= bankspec
329 self
.origsuffix
= origsuffix
or suffix
333 # create consistent name suffixes
334 pingroup
= namesuffix(fname
, suffix
, pingroup
)
340 for name
in pingroup
[:limit
]:
342 name_
= "%s_%s" % (name
, suffix
)
345 if spec
and name
in spec
:
347 pin
= {mux
: (name_
, bank
)}
348 offs_bank
, offs_
= offs
351 idx_
+= bankspec
[bank
]
354 for name
in pingroup
:
356 name_
= "%s_%s" % (name
, suffix
)
363 idx_
, mux_
, bank_
= spec
[name
]
365 pin
= {mux_
: (name_
, bank_
)}
367 res
[idx_
].update(pin
)